参数资料
型号: TMS320VC5409ZGU-80
厂商: Texas Instruments
文件页数: 7/93页
文件大小: 0K
描述: IC FIXED POINT DSP 144-BGA
标准包装: 160
系列: TMS320C54x
类型: 定点
接口: 主机接口,McBSP
时钟速率: 80MHz
非易失内存: ROM(32 kB)
芯片上RAM: 64kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.80V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 144-LFBGA
供应商设备封装: 144-BGA MICROSTAR(12x12)
包装: 托盘
配用: 296-15829-ND - DSP STARTER KIT FOR TMS320C5416
Introduction
15
April 1999 Revised October 2008
SPRS082F
2.4
Terminal Functions
The 5409 Terminal Functions table lists each pin name, function, and operating mode(s) for the 5409 device.
Some of the 5409 pins can be configured for one of two functions; a primary function and a secondary function.
The names of these pins in secondary mode are shaded in grey in Table 22.
Table 22. Terminal Functions
TERMINAL
NAME
INTERNAL
I/O
DESCRIPTION
TERMINAL
NAME
PIN STATE
I/O
DESCRIPTION
DATA SIGNALS
A22
(MSB)
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
(LSB)
Bus holders
available
(A15A0)
O/Z
Parallel address bus A22 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The
lower sixteen address pins (A15 to A0) are multiplexed to address all external memory (program,
data) or I/O while the upper seven address pins (A22 to A16) are only used to address external
program space. These pins are placed in the high-impedance state when the hold mode is enabled,
or when OFF is low.
D15
(MSB)
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
Bus holders
available
I/O/Z
Parallel data bus D15 (MSB) through D0 (LSB). The sixteen data pins (D15 to D0) are multiplexed
to transfer data between the core CPU and external data/program memory or I/O devices. The data
bus is placed in the high-impedance state when not outputting or when RS or HOLD is asserted.
The data bus also goes into the high-impedance state when OFF is low.
The data bus has bus holders to reduce the static power dissipation caused by floating, unused
pins. These bus holders also eliminate the need for external bias resistors on unused pins. When
the data bus is not being driven by the 5409, the bus holders keep the pins at the previous logic level.
The data bus holders on the 5409 are disabled at reset and can be enabled/disabled via the BH bit
of the bank-switching control register (BSCR).
I = Input, O = Output, Z = High-impedance, S = Supply
Although this pin includes an internal pulldown resistor, a 470- external pulldown is required. If the TRST pin is connected to multiple DSPs,
a buffer is recommended to ensure the VIL and VIH specifications are met.
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