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参数资料
| 型号： | TMX320C6415GLS100 |
| 厂商： | Texas Instruments, Inc. |
| 元件分类： | 数字信号处理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 定点数字信号处理器 |
| 文件页数： | 57/70页 |
| 文件大小： | 1050K |
| 代理商： | TMX320C6415GLS100 |
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TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E
OCTOBER 1999
REVISED MARCH 2004
57
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0
(see Figure 35)
200
NO.
MASTER
MIN
12
4
SLAVE
MIN
2
3P
6 + 6P
UNIT
MAX
MAX
4
5
t
su(DRV-CKXL)
t
h(CKXL-DRV)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
ns
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 10b, CLKXP = 0
(see Figure 35)
200
NO.
PARAMETER
MASTER
§
MIN
T
3
L
4
4
SLAVE
MIN
UNIT
MAX
T + 5
L + 5
5
MAX
1
2
3
t
h(CKXL-FXL)
t
d(FXL-CKXH)
t
d(CKXH-DXV)
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
#
Delay time, CLKX high to DX valid
Disable time, DX high impedance following last data bit from
CLKX low
ns
ns
ns
3P + 3
5P + 17
6
t
dis(CKXL-DXHZ)
L
2
L + 3
ns
7
t
dis(FXH-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
P + 3
3P + 17
ns
8
t
d(FXL-DXV)
Delay time, FSX low to DX valid
2P + 2
4P + 17
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§
S =
sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T =
CLKX period = (1 + CLKGDV) * S
H =
CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =
CLKX low pulse width
= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
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相关代理商/技术参数 |
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|---|---|
| TMX320C6415GLW100 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| TMX320C6415GLZ | 制造商:Rochester Electronics LLC 功能描述:320C6415 GLZ KELVIN - Bulk |
| TMX320C6415TGLZ | 功能描述:数字信号处理器和控制器 - DSP, DSC Fixed-Point Digital Signal Processor RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
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| TMX320C6416CGLZ300 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
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