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参数资料
| 型号： | TPD-MR-08-34CDL5A |
| 元件分类： | 光收发 |
| 英文描述： | FIBER OPTIC TRANSCEIVER, 1550-1550nm, 11300Mbps(Tx), 11300Mbps(Rx), PANEL MOUNT, LC CONNECTOR |
| 文件页数： | 8/12页 |
| 文件大小： | 328K |
| 代理商： | TPD-MR-08-34CDL5A |
DS-5710 Rev 012009-11--23
Preliminary Datasheet
TPD-MR-08-34CDL5A
Frequency
tolerance
-100
-
+100
ppm
Rise/Fall time
Tr/Tf
-
500
ps
Duty Cycle
TDC
40
50
60
%
Table 7 - Transmitter/Receiver Parallel Data/Clock Interface
Parameter
Symbol
Level
Notes
Transmitter 16-bit parallel Date Input
TxDin[0:15]P/N
LVDS
TxDin0:LSB, TxDin15:MSB
Transmitter
Source
synchronous
ParallelInput Clock
TxPICLKP/N
LVDS
Transmitter Counter Clock
TxPCLKP/N
LVDS
Receiver 16-bit parallel Date Output
RxDout[0:15]P/N
LVDS
RxDout0:LSB, RxDout15:MSB
Receiver Source synchronous Parallel
Output Clock
RxPOCLKP/N
LVDS
Table 8 - Transmitter/Receiver Parallel Data/Clock Timing
Transmitter Data/Clock Timing: SERDES Input Timing at SERDES pin
Parameter
Symbol
Min.
Typical
Max.
Unit
Notes
TxPICLK
Duty Cycle(TW/TO)
TDC
40
50
60
%
Rise and Fall time
Tr/Tf
100
-
300
ps
20 – 80%
TxDin
Setup time
Ts
250
-
ps
Hold time
Th
250
-
ps
TxPICLKP
TxDin[0:15]P/N
To
Tw
Th
Ts
Ts: Measuring from the LHS inner data eye to the immediate rising edge of clock pulse
Th: Measuring from the rising edge of clock pulse to the inner RHS of data eye
Receiver Data/Clock Timing: SERDES Output Timing at SERDES pin
RxPOCLK
Duty Cycle(TW/TO)
TDC
40
-
60
%
Rise and Fall time
Tr/Tf
100
-
250
ps
20 – 80%
RxDout
Data/Clock skew
Tcq_min,
-
200
ps
Tcq_max
-
200
ps
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