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参数资料
| 型号： | TPD12S521DBTRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO38 |
| 封装： | GREEN, PLASTIC, TSSOP-38 |
| 文件页数： | 7/12页 |
| 文件大小： | 644K |
| 代理商： | TPD12S521DBTRG4 |
SLVS639B – OCTOBER 2007 – REVISED APRIL 2009 .................................................................................................................................................... www.ti.com
PIN DESCRIPTION
NAME
PIN NO.
ESD LEVEL
DESCRIPTION
5V_SUPPLY
1
2 kV(1)
Current source for 5V_OUT
LV_SUPPLY
2
2 kV(1)
Bias for CE/DDC/HOTPLUG level shifters
3, 5, 8, 11,14,
GND, TMDS_GND
NA
TMDS ESD and parasitic GND return(2)
25, 28, 31, 34, 36
TMDS_D2+
4, 35
8 kV(3)
TMDS 0.8-pF ESD protection(4)
TMDS_D2–
6, 33
8 kV(3)
TMDS 0.8-pF ESD protection(4)
TMDS_D1+
7, 32
8 kV(3)
TMDS 0.8-pF ESD protection(4)
TMDS_D1–
9, 30
8 kV(3)
TMDS 0.8-pF ESD protection(4)
TMDS_D0+
10, 29
8 kV(3)
TMDS 0.8-pF ESD protection(4)
TMDS_D0–
12, 27
8 kV(3)
TMDS 0.8-pF ESD protection(4)
TMDS_CK+
13, 26
8 kV(3)
TMDS 0.8-pF ESD protection(4)
TMDS_CK–
15, 24
8 kV(3)
TMDS 0.8-pF ESD protection(4)
CE_REMOTE_IN
16
2 kV(1)
LV_SUPPLY referenced logic level into ASIC
DDC_CLK_IN
17
2 kV(1)
LV_SUPPLY referenced logic level into ASIC
DDC_DAT_IN
18
2 kV(1)
LV_SUPPLY referenced logic level into ASIC
HOTPLUG_DET_IN
19
2 kV(1)
LV_SUPPLY referenced logic level into ASIC
HOTPLUG_DET_OUT
20
8 kV(3)
5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD(5) to connector
DDC_DAT_OUT
21
8 kV(3)
5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector
DDC_CLK_OUT
22
8 kV(3)
5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector
CE_REMOTE_OUT
23
8 kV(3)
5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector
ESD_BYP
37
2 kV(1)
ESD bypass. This pin must be connected to a 0.1-
F ceramic capacitor.
5V_OUT
38
2 kV(1)
5-V regulator output
(1)
Human-Body Model (HBM) per MIL-STD-833, Method 3015, CDISCHARGE = 100 pF, RDISCHARGE = 1.5 k, 5V_SUPPLY and
LV_SUPPLY within recommended operating conitions, GND = 0 V, and ESD_BYP (pin 37) and HOTPLUG_DET_OUT (pin 20) each
bypassed with a 0.1-
F ceramic capacitor connnected to GND.
(2)
These pins should be routed directly to the associated GND pins on the HDMI connector, with single-point ground vias at the connector.
(3)
Standard IEC 61000-4-2, CDISCHARGE = 150 pF, RDISCHARGE = 330 , 5V_SUPPLY and LV_SUPPLY within recommended operating
conditions, GND = 0 V, and ESD_BYP (pin 37) and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1-
F ceramic capacitor
connected to GND.
(4)
These two pins must be connected together inline on the PCB.
(5)
This output can be connected to an external 0.1-
F ceramic capacitor, resulting in an increased ESD withstand voltage rating.
4
Copyright 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): TPD12S521
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