ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATING TABLE
SLVS798F – JANUARY 2008 – REVISED NOVEMBER 2008 ........................................................................................................................................... www.ti.com
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields.
These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to
MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to these high-impedance circuits. During storage or handling the device leads should be shorted together
or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate logic
voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication
Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
AVAILABLE OPTION AND ORDERING INFORMATION
PACKAGE(1)
RECOMMENDED
TYPICAL
MAXIMUM
D-8
DRB-8
TA
ENABLE
SHORT-CIRCUIT
CONTINUOUS LOAD
(SOIC)
(SON)
LIMIT
CURRENT
PART #
STATUS
PART #
STATUS
Active
TPS2062AD
AVAILABLE
TPS2062ADRB
AVAILABLE
low
–40°C to
1 A
1.6 A
85°C
Active
TPS2066AD
AVAILABLE
TPS2066ADRB
AVAILABLE
high
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
over operating temperature range unless otherwise noted
(1) (2)
VALUE
UNIT
VI
Input voltage range
IN
–0.3 to 6
V
VO
Output voltage range
OUTx
–0.3 to 6
V
Input voltage range
ENx, ENx
–0.3 to 6
V
VI
Voltage range
OCx
–0.3 to 6
V
IO
Continuous output current
OUTx
Internally limited
Continuous total power dissipation
See "Dissipation Rating Table"
TJ
Operating junction temperature range
–40 to 125
°C
Tstg
Storage temperature range
–65 to 150
°C
Human body model MIL-STD-883C
2
kV
Electrostatic discharge
ESD
protection
Charge device model (CDM)
500
V
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
All voltages are with respect to GND.
TA ≤ 25°C
DERATING
TA = 70°C
TA = 85°C
THERMAL
POWER
FACTOR
POWER
BOARD
PACKAGE
RESISTANCE
θ
JA
RATING
ABOVE TA =
RATING
25°C
Low-K(1)
D-8
170 °C/W
586 mW
5.86 mW/°C
320 mW
234 mW
High-K(2)
D-8
97.5 °C/W
1025 mW
10.26 mW/°C
564 mW
410 mW
Low-K(3)
DRB(4)
270 °C/W
370 mW
3.71 mW/°C
203 mW
148 mW
High-K(5)
DRB(4)
60 °C/W
1600 mW
16.67 mW/°C
916 mW
666 mW
(1)
The JEDEC low-K (1s) board used to dervie this data was a 3in x 3in, two-layer board with 2-ounce copper traces on top of the board.
(2)
The JEDEC high-K (2s2p) board used to dervive this data was a 3in x 3in, multilayer board with 1-ounce internal power and ground
planes and 2-ounce copper traces on top and bottom of the board.
(3)
Soldered PowerPAD on a standard 2-layer PCB without vias for thermal pad. See TI application note SLMA002 for further details.
(4)
See Recommended Operating Conditions Table for PowePad connection guidelines to meet qualifying conditions for CB Certificate
(5)
Soldered PowerPAD on a standard 4-layer PCB with vias for thermal pad. See TI application note SLMA002 for further details.
2
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