参数资料
型号: TPS2214DB
厂商: Texas Instruments
文件页数: 21/25页
文件大小: 0K
描述: IC DUAL PCMCIA PWR SW 24-SSOP
标准包装: 60
类型: PCMCIA/Cardbus 开关
输出数: 2
Rds(开): 105 毫欧
内部开关:
电流限制: 1A
输入电压: 3.3V,5V,12V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-SSOP(0.209",5.30mm 宽)
供应商设备封装: 24-SSOP
包装: 管件
产品目录页面: 1043 (CN2011-ZH PDF)
其它名称: 296-2249-5
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206B – JULY 1999 – REVISED JUNE 2000
APPLICATION INFORMATION
power supply considerations
The TPS2214 has multiple pins for each of its 3.3-V and 5-V power inputs and for the switched xVCC outputs.
Any individual pin can conduct the rated input or output current. Unless all pins are connected in parallel, the
series resistance is higher than that specified, resulting in increased voltage drops and less power. It is
recommended that all input and output power pins be paralleled for optimum operation. Because the two 12-V
pins are not internally connected, they must be tied together externally.
To increase the noise immunity of the TPS2214, the power-supply inputs should be bypassed with a 1- μ F
electrolytic or tantalum capacitor paralleled by a 0.047- μ F to 0.1- μ F ceramic capacitor. It is strongly
recommended that the switched outputs be bypassed with a 0.1- μ F (or larger) ceramic capacitor; doing so
improves the immunity of the IC to electrostatic discharge (ESD). Care should be taken to minimize the
inductance of PCB traces between the IC and the load. High switching currents can produce large negative
voltage transients, which forward biases substrate diodes, resulting in unpredictable performance. Similarly, no
pin should be taken, or allowed to fall, below – 0.3 V.
RESET and RESET inputs
To ensure that cards are in a known state after power brownouts or system initialization, the PC Cards should
be reset at the same time as the host by applying low impedance paths from xVCC and xVPP terminals to
ground. A low-impedance output state allows discharging of residual voltage remaining on PC Card filter
capacitance, permitting the system (host and PC Cards) to be powered up concurrently. The active-high RESET
or active low RESET input will close internal switches S1, S4, S7, and S11 with all other switches left open. The
TPS2214 remains in the low-impedance output state until the signal is deasserted and further data is clocked
in and latched. The input serial data can not be latched during Reset mode. RESET and RESET are provided
for direct compatibility with systems that use either an active-low or active-high reset voltage supervisor. The
RESET pin has an internal 150-k ? pulldown resistor and the RESET pin has an internal 150-k ? pullup resistor.
The device will be reset automatically when powered up.
calculating junction temperature
The switch resistance, r DS(on) , is dependent on the junction temperature, T J , of the die. The junction temperature
is dependent on both r DS(on) and the current through the switch. To calculate T J , first find r DS(on) from Figures 23
through 26, using an initial temperature estimate about 50 ° C above ambient. Then calculate the power
dissipation for each switch, using the formula:
P
D
r
DS(on)
I2
Next, sum the power dissipation of all switches and calculate the junction temperature:
T
J
P
D
R
JA
T
A
Where:
R θ JA is the inverse of the derating factor given in the dissipation rating table.
Compare the calculated junction temperature with the initial temperature estimate. If the temperatures are not
within a few degrees of each other, recalculate using the calculated temperature as the initial estimate.
logic inputs and outputs
The serial interface consists of DATA, CLOCK, and LATCH leads. The data is clocked in on the positive edge
of the clock (see Figures 2 and 3). The 11-bit (D0 – D10) serial data word is loaded during the positive edge of
the latch signal. The positive edge of the latch signal should occur before the next positive edge of the clock
occurs.
POST OFFICE BOX 655303
? DALLAS, TEXAS 75265
21
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