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参数资料
| 型号： | TPS2223DB |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | 3-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO24 |
| 封装： | GREEN, PLASTIC, SSOP-24 |
| 文件页数： | 30/33页 |
| 文件大小： | 814K |
| 代理商： | TPS2223DB |
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TPS2223, TPS2224, TPS2226
DUALSLOT CARDBUS POWERINTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS317 MAY 2001
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics, TJ = 25°C, VI(5V) = 5 V, VI(3.3V) = 3.3 V, VI(12V) = 12 V (not applicable for
TPS2223), all outputs unloaded (unless otherwise noted) (continued)
logic section (CLOCK, DATA, LATCH, RESET, SHDN, OC)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
II(/RESET) (see Note 2)
RESET = 5.5 V
1
II(/RESET) (see Note 2)
RESET = 0 V
30
20
10
II(/SHDN) (see Note 2)
SHDN = 5.5 V
1
II
Input current, logic
II(/SHDN) (see Note 2)
SHDN = 0 V
50
3
A
II
Input current, logic
II(LATCH) (see Note 2)
LATCH = 5.5 V
50
A
II(LATCH) (see Note 2)
LATCH = 0 V
1
II(CLOCK, DATA)
0 V to 5.5 V
1
VIH
High-level input voltage, logic
2
V
VIL
Low-level input voltage, logic
0.8
V
VO(sat)
Output saturation voltage at OC
IO = 2 mA
0.14
0.4
V
Ilkg
Leakage current at OC
VO(/OC) = 5.5 V
0
1
A
NOTE 2: LATCH has low current pulldown. RESET and SHDN have low-current pullup.
UVLO and POR (power-on reset)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI(3.3V)
Input voltage at 3.3V pin, UVLO
3.3 V level below which all switches are Hi-Z
2.4
2.7
2.9
V
Vhys(3.3V)
UVLO hysteresis voltage at VA
(see Note 1)
70
100
mV
VI(5V)
Input voltage at 5V pin, UVLO
5 V level below which only 5V switches are Hi-Z
2.3
2.5
2.9
V
Vhys(5V)
UVLO hysteresis voltage at 5V
(see Note 1)
70
100
mV
tdf
Delay time for falling response, UVLO
(see Note 1)
Delay from voltage hit (step from 3 V to 2.3 V)
to Hi-Z control (90% VG to GND)
4
s
VI(POR)
Input voltage, power-on reset
(see Note 1)
3.3 V voltage below which POR is asserted
causing a RESET internally with all line
switches open and all discharge switches
closed.
1.7
V
NOTE 1: Specified by design; not tested in production.
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