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参数资料
| 型号： | TPS2383PMR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP64 |
| 封装： | GREEN, PLASTIC, LQFP-64 |
| 文件页数： | 8/28页 |
| 文件大小： | 397K |
| 代理商： | TPS2383PMR |
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TPS2383
SLUS559B APRIL 2003 REVISED JULY 2004
16
www.ti.com
FUNCTIONAL DESCRIPTION
Data Read Cycle
For a data read sequence, after the register acknowledge bit, the master device generates a Stop condition.
This is followed by a second Start condition, and retransmitting the device address as described in Chip Address
above. For this cycle, however, the R/W bit is set to a 1 to signal the read operation. The TPS2383 again
responds with an acknowledge pulse. The address acknowledge is then followed by sequentially presenting
each of the eight data bits on the SDA line (MSB first), to be read by the host device on the rising edges of SCL.
After eight bits are transmitted, the host acknowledges by pulling the SDA line high for one clock pulse. The
completed data transfer is terminated with the host generating a Stop condition.
Table 2. Register/Port Addressing
BIT
FUNCTION
STATE
D7
Future expansion
D6
Future expansion
D5
R2, register select MSB
000
= Control (common Write register)
001
= Port Status (per port Read register)
D4
R1, register select
001
= Port Status (per port Read register)
010
= Port Control (per port Write register)
011
= A2D Register low byte (common read register)
D3
R0, register select LSB
011
= A2D Register low byte (common read register)
100
= A2D Register high byte (common read register)
101
= Chip identification/revision (common read register)
D2
P2, port address MSB
000
= Port 1
001
= Port 2
010
= Port 3
D1
P1, port address
010
= Port 3
011
= Port 4
100
= Port 5
= Port 6
D0
P0, port address LSB
= Port 5
101
= Port 6
110
= Port 7
111
= Port 8
Port/Register Cycle
Table 3. Common Control
Write Register, Register Address = 000 (Common Register)
BIT
FUNCTION
STATE
PRESET
STATE
D7
Jog_mode
0
= Normal mode
1
= Jog mode
0
D6
Jog
0
= Don’t jog
1
= Jog. This bit is self-clearing. It does not need to be reset to a 0 for each new jog.
0
D5
Bypass ramp
0
= Normal mode
1
= Bypass powerup ramp and powered mode for all ports
0
D4
Disconnect disable
0
= Normal mode
1
= Disable the effect of the logic signal from the Disconnect detection circuits. This is
an expansion function for future parts. This bit should be set to a logic 1
0
D3
Bypass discovery
0
= Normal mode
1
= Bypass discovery mode.
0
D2
Bypass sample
0
= Normal mode
1
= Bypass current sample of all powered ports.
0
D1
Bypass classification
0
= Normal mode
1
= Bypass classification of all ports.
0
D0
Discovery fault disable
0
= Normal mode
1
= Disable the effect of the logic signal from the Discovery circuits. This is
an expansion function for future parts. This bit should be set to a logic 1.
0
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