参数资料
型号: TPS2399DGKRG4
厂商: TEXAS INSTRUMENTS INC
元件分类: 电源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8
封装: GREEN, PLASTIC, MSOP-8
文件页数: 5/27页
文件大小: 792K
代理商: TPS2399DGKRG4
TPS2398
TPS2399
SLUS562A JUNE 2003 REVISED SEPTEMBER 2003
13
www.ti.com
APPLICATION INFORMATION
Subsequent to a plug-in’s start-up, and during the module’s steady-state operation, load faults that force current
limit operation also initiate fault timing cycles as described above. In this case, a fault timeout also clears the
previously latched power good status.
The TPS2398 latches off in response to faults; once a fault timeout occurs, the DCHG signal turns on a large
NMOS device to rapidly discharge the external capacitor, resetting the timer for any subsequent device reset.
The TPS2398 can only be reset by cycling power to the device, or by cycling the EN input.
In response to a latched fault condition, the TPS2399 enters a fault retry mode, wherein it periodically retries
the load to test for continued existence of the fault. In this mode, the FLTTIME capacitor is discharged slowly
by a about a 0.4-
A constant-current sink. When the voltage at the FLTTIME pin decays below 0.5 V, the LCA
and RAMP CONTROL circuits are re-enabled, and a normal turn-on current ramp ensues. Again, during the
load charging, the OC signal causes charging of the FLTTIME capacitor until the next delay period elapses. The
sequential charging and discharging of the FLTTIME capacitor results in a typical 1% retry duty cycle. If the fault
subsides, the timing capacitor is rapidly discharged, duty-cycle operation stops, and the PG output is asserted.
Note that because of the timing inhibit during the initial slow ramp period, the duty cycle in practice is slightly
greater than the nominal 1% value. However, sourced current during this period peaks at only about one-eighth
the maximum limit. The duty cycle of the normal ramp and constant-current periods is approximately 1%.
The FAULT LOGIC within the TIMER BLOCK automatically manages capacitor charge and discharge actions,
and the enabling of the GATE output (DCHG and ON signals).
supply transient response
The TPS2398 and TPS2399 also feature a fast-acting overload comparator which acts to clamp large transients
from catastrophic faults occurring once the pass FET is fully enhanced, such as short circuits. This function
provides a back-up protection to the LCA by providing a hard gate discharge action when the LCA is saturated.
If sense voltage excursions above 100 mV are detected, this comparator rapidly pulls down the GATE output,
bypassing the fault timer, and terminating the shortcircuit condition. Once the spike has been brought down
below the overload threshold, the GATE output is released, allowing the circuit to turn on again in either
current-ramp or current-limit mode. A 4
s deglitch filter is applied to the OL signal to help reduce the
occurrence of nuisance trips.
In redundant-supply systems, the sudden switchover to a supply of higher voltage potential is one more source
of large current spikes. Due to the low impedance of filter capacitance under such high-frequency transients,
these spikes are generally indistinguishable from true short-circuit faults to a hot swap controller. However, the
TPS2398and TPS2399 transient response addresses this issue by providing rapid circuit-breaker protection
for load faults along with minimal interruption of power flow during supply switching events. The scope plots in
Figure 20 illustrate how.
Figure 20 is a scope capture of the TPS2398/99 response in a diode-OR configuration to such an input transient
event. (All waveforms are referenced to the VIN pin.) In this example, the module is initially operating from
a nominal 44-V supply (relative to the backplane supply return node). At the second major time division,
another power supply, with an output of 48 V, is suddenly hot swapped into a secondary, or INB, input. This
sudden voltage step is reflected in the 48V_RTN trace. On this board, the 4V potential difference caused
a greater than 6-A spike, as shown by the IINB trace. The GATE pin is rapidly pulled low, which quickly terminates
the overload spike. However, it is quickly released, and seen to drive back to the pass FET ON-threshold, in
this case, about 4.5 V. The resultant current-limit operation of the circuit is evidenced by the 2-A load on the B
supply. Once supply current is flowing again, the filter capacitance is charged up to the new input supply level,
seen here on the VDRAIN trace. Once the capacitance is fully charged, the load demand rolls off to the operating
1-A level. As an added benefit, this event is transparent to the PG signal, which remains asserted throughout
the disturbance.
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