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参数资料
| 型号： | TPS2491DGSG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO10 |
| 封装： | GREEN, PLASTIC, MSOP-10 |
| 文件页数： | 4/24页 |
| 文件大小： | 534K |
| 代理商： | TPS2491DGSG4 |
VCC OUT
10V/div
VOUT10V/div
IIN
1A/div
FETPWR10W/div
M1PowerMeasured29.6W,
Calculated34.4W
t-Time-2ms/div
SLVS503C
– NOVEMBER 2003 – REVISED SEPTEMBER 2011
Action of the Constant Power Engine (Figure 14)
The calculated power dissipated in M1, VDS ×ID, is computed under the same startup conditions as
. The current of M1, labeled IIN, initially rises to the value that satisfies the constant
power
engine;
in
this
case
it
is
34 W
÷ 48 V = 0.7 A. The 34 W value is programmed into the engine by setting the PROG voltage using the
equation given in the PROG pin description. VDS of M1, which is calculated as V(SENSE–OUT), falls as CO charges,
thus allowing the M1 drain current to increase
. This is the result of the internal constant power engine
adjusting the current limit reference to the GATE amplifier as CO charges and VDS falls. The calculated device
power in Figure 14, labeled FET PWR, is seen to be flat-topped and constant within the limitations of circuit
tolerance and acquisition noise. A fixed current limit is implemented by clamping the constant power engine
’s
output to 50 mV when VDS is low. This protection technique can be viewed as a specialized form of foldback
limiting; the benefit over linear foldback is that it yields the maximum output current from a device over the full
range of VDS and still protects the device.
Figure 14. Computation of M1 Stress During Startup
Figure 15 shows the short circuit response over the full time-out period. The period begins when the output
voltage falls and ends when M1 is turned off. M1 current is actively controlled by the constant power engine and
gate amplifier circuit while the TIMER pin charges CT to the 4 V threshold causing M1 to be turned off. The
TPS2490 latches off after the threshold is reached until either the input voltage drops below the UVLO threshold
or EN cycles through the false (low) state. The TPS2491 goes through a timing sequence before attempting a
restart.
12
Copyright
2003–2011, Texas Instruments Incorporated
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