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参数资料
| 型号： | TPS3600D50PWR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14 |
| 封装： | 5.10 X 6.60 MM, GREEN, PLASTIC, TSSOP-14 |
| 文件页数： | 5/26页 |
| 文件大小： | 677K |
| 代理商： | TPS3600D50PWR |
TPS3600D20, TPS3600D25, TPS3600D33, TPS3600D50
BATTERY BACKUP SUPERVISORS FOR LOW POWER PROCESSORS
SLVS336B DECEMBER 2000 REVISED JANUARY 2007
13
timing requirements at RL = 1 M, CL = 50 pF, TA = 40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD
VIH = VIT + 0.2 V, VIL = VIT 0.2 V
5
1
s
tw
Pulse width
MR
VDD > VIT + 0.2 V, VIL = 0.3 x VDD, VIH = 0.7 x VDD
100
ns
tw
Pulse width
WDI
VDD > VIT + 0.2 V, VIL = 0.3 x VDD, VIH = 0.7 x VDD
100
ns
switching characteristics at RL= 1 M, CL = 50 pF, TA = 40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
td
Delay time
VDD ≥ VIT + 0.2 V,
MR
≥ 0.7 x VDD,
See timing diagram
60
100
140
ms
t(tout) Watchdog time-out
VDD > VIT + 0.2 V,
See timing diagram
0.48
0.8
1.12
s
tPLH
Propagation (delay) time,
low-to-high-level output
50% RESET to 50% CEOUT
VOUT = VIT
15
s
VDD to RESET
VIL = VIT 0.2 V,
VIH = VIT + 0.2 V
2
5
s
PFI to PFO
VIL = V(PFI) 0.2 V,
VIH = V(PFI) + 0.2 V
3
5
s
tPHL
Propagation (delay) time,
high-to-low-level output
MR to RESET
VDD ≥ VIT + 0.2 V,
VIL = 0.3 x VDD,
VIH = 0.7 x VDD
0.1
1
s
50% CEIN to 50% CEOUT
VDD = 1.8 V
5
15
ns
50% CEIN to 50% CEOUT
CL = 50 pF only (see Note 6)
VDD = 3.3 V
1.6
5
ns
CL = 50 pF only (see Note 6)
VDD = 5 V
1
3
ns
Transition time
VDD to BATTON
VIL = VBAT 0.2 V,
VIH = VBAT + 0.2 V,
V(BAT) < VIT
3
s
NOTE 6: Ensured by design.
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Static Drain-source on-state resistance VDD to VOUT
vs Output current
5
rDS(on)
Static Drain-source on-state resistance VBAT to VOUT
vs Output current
6
rDS(on)
Static Drain-source on-state resistance
vs Chip enable input voltage
7
IDD
Supply current
vs Supply voltage
8, 9
VIT
Normalized threshold voltage
vs Free-air temperature
10
High-level output voltage at RESET
11, 12
VOH
High-level output voltage at PFO
vs High-level output current
13, 14
VOH
High-level output voltage at CEOUT
vs High-level output current
15, 16, 17, 18
Low-level output voltage at RESET
19, 20
VOL
Low-level output voltage at CEOUT
vs Low-level output current
21, 22
VOL
Low-level output voltage at BATTON
vs Low-level output current
23, 24
tp(min)
Minimum Pulse Duration at VDD
vs Threshold voltage overdrive at VDD
25
tp(min)
Minimum Pulse Duration at PFI
vs Threshold voltage overdrive at PFI
26
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