参数资料
型号: TPS3606-33DGSR
厂商: TEXAS INSTRUMENTS INC
元件分类: 电源管理
英文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO10
封装: GREEN, PLASTIC, MSOP-10
文件页数: 18/18页
文件大小: 507K
代理商: TPS3606-33DGSR
TPS360633
BATTERY BACKUP SUPERVISOR FOR LOW POWER PROCESSORS
SLVS335C DECEMBER 2000 REVISED JANUARY 2007
9
electrical characteristics over recommended operating conditions (unless otherwise noted)
(continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.65 V
< VIT < 2.5 V
20
VIT
2.5 V
< VIT < 3.5 V
40
VIT
3.5 V
< VIT < 5.5 V
50
Vhys
Hysteresis
VPFI
12
mV
Vhys
Hysteresis
1.65 V
< V(SWN) < 2.5 V
85
mV
V(SWN)
2.5 V
< V(SWN) < 3.5 V
100
V(SWN)
3.5 V
< V(SWN) < 5.5 V
110
IIH
High-level input current
WDI
WDI = VDD = 5.5 V
150
A
IIH
High-level input current
MR
MR = 0.7
× VDD, VDD = 5 V
33
76
IIL
Low-level input current
WDI
WDI = 0 V,
VDD = 5 V
150
IIL
Low-level input current
MR
MR = 0 V,
VDD = 5 V
110
255
II
Input current
PFI, MSWITCH
VI < VDD
25
nA
PFO = 0 V,
VDD = 1.8 V
0.3
IOS
Short-circuit current
PFO
PFO = 0 V,
VDD = 3.3 V
1.1
mA
IOS
Short-circuit current
PFO
PFO = 0 V,
VDD = 5 V
2.4
mA
IDD
VDD supply current
VOUT = VDD
40
A
IDD
VDD supply current
VOUT = VBAT
8
A
I(BAT)
VBAT supply current
VOUT = VDD
0.1
A
I(BAT)
VBAT supply current
VOUT = VBAT
40
A
Ci
Input capacitance
VI = 0 V to 5 V
5
pF
timing requirements at RL = 1 M, CL = 50 pF, TA = 40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD
VIH = VIT + 0.2 V, VIL = VIT 0.2 V
5
s
tw
Pulse width
MR
VDD > VIT + 0.2 V, VIL = 0.3 x VDD, VIH = 0.7 x VDD
100
ns
tw
Pulse width
WDI
VDD > VIT + 0.2 V, VIL = 0.3 x VDD, VIH = 0.7 x VDD
100
ns
switching characteristics at RL= 1 M, CL = 50 pF, TA = 40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
td
Delay time
VDD ≥ VIT + 0.2 V,
MR
≥ 0.7 x VDD,
See timing diagram
60
100
140
ms
t(tout)
Watchdog time-out
VDD > VIT + 0.2 V,
See timing diagram
0.48
0.8
1.12
s
VDD to RESET
VIL = VIT 0.2 V,
VIH = VIT + 0.2 V
2
5
s
tPHL
Propagation (delay) time,
high-to-low-level output
PFI to PFO
VIL = V(PFI) 0.2 V, VIH = V(PFI) + 0.2 V
3
5
s
tPHL
Propagation (delay) time,
high-to-low-level output
MR to RESET
VDD ≥ VIT + 0.2 V,
VIL = 0.3 x VDD,
VIH = 0.7 x VDD
0.1
1
s
Transition time
VDD to VBAT
VIL = V(BAT) 0.2 V, VIH = V(BAT) + 0.2 V,
V(BAT) < VIT
3
s
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