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参数资料
| 型号： | TPS3808G30DRVR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO6 |
| 封装： | 2 X 2 MM, GREEN, PLASTIC, SON-6 |
| 文件页数： | 17/23页 |
| 文件大小： | 708K |
| 代理商： | TPS3808G30DRVR |
ELECTRICAL CHARACTERISTICS
www.ti.com .......................................................................................................................................................... SBVS050J – MAY 2004 – REVISED AUGUST 2008
1.7V
≤ VDD ≤ 6.5V, RLRESET = 100k, CLRESET = 50pF, over operating temperature range (TJ = –40°C to +125°C), unless
otherwise noted. Typical values are at TJ = +25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
–40°C < TJ < +125°C
1.7
6.5
VDD
Input supply range
V
0°C < TJ < +85°C
1.65
6.5
VDD = 3.3V, RESET not asserted
2.4
5.0
A
MR, RESET, CT open
IDD
Supply current (current into VDD pin)
VDD = 6.5V, RESET not asserted
2.7
6.0
A
MR, RESET, CT open
1.3V
≤ VDD < 1.8V, IOL = 0.4mA
0.3
V
VOL
Low-level output voltage
1.8V
≤ VDD ≤ 6.5V, IOL = 1.0mA
0.4
V
Power-up reset voltage(1)
VOL (max) = 0.2V, IRESET = 15A
0.8
V
TPS3808G01
–2.0
±1.0
+2.0
VIT ≤ 3.3V
–1.5
±0.5
+1.5
Negative-going
VIT
input threshold
3.3V < VIT ≤ 5.0V
–2.0
±1.0
+2.0
%
accuracy
VIT ≤ 3.3V
–40°C < TJ < +85°C
–1.25
±0.5
+1.25
3.3V < VIT ≤ 5.0V
–40°C < TJ < +85°C
–1.5
±0.5
+1.5
TPS3808G01
1.5
3.0
VHYS
Hysteresis on VIT pin
–40°C < TJ < +85°C
1.0
2.0
%VIT
Fixed versions
1.0
2.5
RMR
MR Internal pull-up resistance
70
90
k
TPS3808G01
VSENSE = VIT
–25
25
nA
Input current at
ISENSE
SENSE pin
Fixed versions
VSENSE = 6.5V
1.7
A
IOH
RESET leakage current
VRESET = 6.5V, RESET not asserted
300
nA
CT pin
VIN = 0V to VDD
5
Input capacitance,
CIN
pF
any pin
Other pins
VIN = 0V to 6.5V
5
VIL
MR logic low input
0
0.3 VDD
V
VIH
MR logic high input
0.7 VDD
VDD
SENSE
VIH = 1.05VIT, VIL = 0.95VIT
20
Input pulse width
tw
s
to RESET
MR
VIH = 0.7VDD, VIL = 0.3VDD
0.001
CT = Open
12
20
28
ms
CT = VDD
180
300
420
ms
td
RESET delay time
See Timing Diagram
CT = 100pF
0.75
1.25
1.75
ms
CT = 180nF
0.7
1.2
1.7
s
Propagation delay
MR to RESET
VIH = 0.7VDD, VIL = 0.3VDD
150
ns
tpHL
High to low level
SENSE to RESET
VIH = 1.05VIT, VIL = 0.95VIT
20
s
RESET delay
θ
JA
Thermal resistance, junction-to-ambient
290
°C/W
(1)
The lowest supply voltage (VDD) at which RESET becomes active. Trise(VDD) ≥ 15s/V.
Copyright 2004–2008, Texas Instruments Incorporated
3
Product Folder Link(s): TPS3808
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