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参数资料
| 型号： | TPS3818G125DRVT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO6 |
| 封装： | 2 X 2 MM, PLASTIC, SON-6 |
| 文件页数： | 12/17页 |
| 文件大小： | 579K |
| 代理商： | TPS3818G125DRVT |
+
-
SENSE
MR
+
-
0.4V
V
REF
AdjustableVoltageVersion
FixedVoltageVersion
90kW
TPS3818G01
AdjustableVoltage
Reset
Logic
Timer
RESET
C
T
V
DD
GND
0.4V
V
REF
V
DD
MR
90kW
Reset
Logic
Timer
RESET
C
T
V
DD
GND
V
DD
SENSE
R
2
R +R
2
1
=4MW
R
1
PIN ASSIGNMENTS
RESET
GND
MR
6
5
4
V
DD
SENSE
C
T
1
2
3
Power
PAD
V
DD
SENSE
C
T
RESET
GND
MR
1
2
3
6
5
4
SBVS106A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com
FUNCTIONAL BLOCK DIAGRAMS
Figure 1. Adjustable and Fixed Voltage Versions
DBV PACKAGE
DRV PACKAGE
SOT23
2mm × 2mm QFN
(TOP VIEW)
Table 1. TERMINAL FUNCTIONS
TERMINAL
SOT23 (DBV)
NAME
PIN NO.
DESCRIPTION
RESET
1
RESET is an open-drain output that is driven to a low impedance state when RESET is asserted (either the
SENSE input is lower than the threshold voltage (VIT) or the MR pin is set to a logic low). RESET remains
low (asserted) for the reset period after both SENSE is above VIT and MR is set to a logic high. A pull-up
resistor from 10k
to 1M should be used on this pin, and allows the reset pin to attain voltages higher than
VDD.
GND
2
Ground
MR
3
Driving the manual reset pin (MR) low asserts RESET. MR is internally tied to VDD by a 90k pull-up
resistor.
CT
4
Reset period programming pin. Connecting this pin to VDD through a 40k to 200k resistor or leaving it
open results in fixed delay times (see Electrical Characteristics). Connecting this pin to a ground referenced
capacitor
≥ 100pF gives a user-programmable delay time. See the Selecting the Reset Delay Time section
for more information.
SENSE
5
This pin is connected to the voltage to be monitored. If the voltage at this terminal drops below the threshold
voltage VIT, then RESET is asserted.
VDD
6
Supply voltage. It is good analog design practice to place a 0.1
F ceramic capacitor close to this pin.
PowerPAD
PowerPAD. Connect to ground plane to enhance thermal performance of package.
4
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS3818
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