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| 型号： | TPS40070PWP |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 2 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封装： | GREEN, PLASTIC, HTSSOP-16 |
| 文件页数： | 27/28页 |
| 文件大小： | 655K |
| 代理商： | TPS40070PWP |
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C u
V
IN * 8 V
R
SR
(1)
R t
0.2 V
f
SW
Q
g(TOT) ) IDD
(2)
SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR)
R
T +
1
f
SW(kHz)
17.82
10*6
* 23
kW
(3)
100
1.5
0.5
1000
200
300
400 500
600
700
800 900
1.0
3.0
2.0
2.5
4.5
3.5
4.0
5.0
MINIMUM OUTPUT VOLTAGE
vs
FREQUENCY
fOSC - Oscillator Frequency - kHz
V
O
U
T
-
Output
V
oltage
-
V
VIN = 28 V
VIN = 24 V
VIN = 18 V
VIN = 15 V
VIN = 12 V
VIN = 10 V
VIN = 8 V
VIN = 5 V
fSW - Switching Frequency - kHz
SWITCHING FREQUENCY
vs
TIMING RESISTANCE
0
100
0
200
400
600
800
1000
200
300
400
500
600
R
T
-
T
iming
Resistance
-
k
PROGRAMMING THE RAMP GENERATOR CIRCUIT AND UVLO
SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 .................................................................................................................................................. www.ti.com
where
V
VIN is the final value of the input voltage ramp
f
SW is the switching frequency
Q
g(TOT) is the combined total gate charge for both upper and lower MOSFETs (from MOSFET data sheet)
I
DD is the TPS4007x input current (3.5 mA maximum)
SR is the maximum allowed slew rate [12×104] (V/s)
The TPS4007x has independent clock oscillator and PWM ramp generator circuits. The clock oscillator serves as
the master clock to the ramp generator circuit. Connecting a single resistor from RT to ground sets the switching
frequency of the clock oscillator. The clock frequency is related to RT by:
Figure 2.
Figure 3.
The ramp generator circuit provides the actual ramp used by the PWM comparator. The ramp generator provides
voltage feed-forward control by varying the PWM ramp slope with line voltage, while maintaining a constant ramp
magnitude. Varying the PWM ramp directly with line voltage provides excellent response to line variations since
the PWM does not have to wait for loop delays before changing the duty cycle. (See Figure 9).
The PWM ramp must reach approximately 1 V in amplitude during a clock cycle, or the PWM is not allowed to
start. The PWM ramp time is programmed via a single resistor (RKFF) connected from KFF VDD. RKFF , VSTART
and RT are related by (approximately):
8
Copyright 2003–2009, Texas Instruments Incorporated
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