参数资料
型号: TPS40131RHBR
厂商: TEXAS INSTRUMENTS INC
元件分类: 稳压器
英文描述: SWITCHING CONTROLLER, 1200 kHz SWITCHING FREQ-MAX, PQCC32
封装: GREEN, PLASTIC, QFN-32
文件页数: 11/40页
文件大小: 940K
代理商: TPS40131RHBR
www.ti.com
DESIGN EXAMPLE
Two Phase Single Output Configuration from 12 V to 1.5 V DC/DC Converter Using a TPS40131
Setp 1: Inductor Selection
IN(max)
OUT
RIPPLE
IN(max)
SW
V
1
L
I
V
f
-
=
(15)
Step 2: Output Capacitor Slection
(
)
(
)
2
TRAN(max)
OUT(min)
IN(min)
OUT
UNDER
1
I
L
2
C
V
=
-
(16)
(
)
(
)
2
TRAN(max)
OUT(min)
OUT
OVER
1
I
L
2
C
V
=
(17)
OUT
1
2
D
2
D
I
(D)
1
2
D
1
-
-
D
=
-
+
(18)
SLVS635 – FEBRUARY 2007
The following example illustrates the design process and component selection for a two phase single output
synchronous buck converter using TPS40131. The design goal parameters are given in the table below.
Design Goal Parameters
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
Input voltage
10.8
12.0
13.2
V
VOUT
Output voltage
1.5
VRIPPLE
Output ripple
IOUT = 40 A
30
mV
IOUT
Output current
40
A
fSW
Switching frequency
350
kHz
The inductor is determined by the desired ripple current. The required inductor is calculated using Equation 15.
Typically the peak-to-peak inductor current IRIPPLE is selected to be around 20% of the rated output current. In
this design, IRIPPLE is targeted at 23% of IPHASE. The calculated inductor is 0.815 μH and in practical a 0.82-μH,
30-A inductor with 2-m
DCR from Vishay is selected. The real inductor ripple current is 4.63 A.
The output capacitor is typically selected by the output load transient response requirement. Equation 16
estimates the minimum capacitor to reach the undervoltage requirement with load step up. Equation 17
estimates the minimum capacitor for overvoltage requirement with load step down. When VIN(min) < 2×VOUT, the
minimum output capacitance can be calculated using Equation 16. Otherwise, Equation 17 is used.
In this design, VIN(min) is much larger than 2 × VOUT, so Equation 17 is used to determine the minimum
capacitance. Based on a 15-A load transient with a maximum of 80-mV deviation, a minimum 1-mF output
capacitor is required. In the design, six 180-
μF, 6.3-V SP capacitors are selected to meet this requirement. Each
capacitor has an ESR of 5 m
.
Due to the interleaving of channels, the total output ripple current is smaller than the ripple current from a single
phase. The ripple cancellation factor is expressed in Equation 18.
where
D is the duty cycle for a single phase
The maximum output ripple current is calculated in Equation 19.
19
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