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| 型号： | TPS40195RGYR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 580 kHz SWITCHING FREQ-MAX, PQCC16 |
| 封装： | GREEN, PLASTIC, QFN-16 |
| 文件页数： | 7/43页 |
| 文件大小： | 1086K |
| 代理商： | TPS40195RGYR |
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ON
OFF
UVLO
V
R1
I
-
=
(2)
UVLO
ON
UVLO
V
R2
R1
V
=
-
(3)
5
R1
R2
V
IN
+
BP
UVLO
1.26 V
I
UVLO
5.2 mA (typ)
UDG-07002
Soft Start
www.ti.com ........................................................................................................................................ SLUS720D – FEBRUARY 2007 – REVISED NOVEMBER 2008
where
V
ON is the desired turn on voltage of the converter
V
OFF is the desired turn off voltage for the converter, must be less than VON
I
UVLO is the hysteresis current generated by the device, 5.2 A (typ)
V
UVLO is the UVLO pin threshold voltage, 1.26 V (typ)
Figure 20. Undervoltage Lockout
The TPS40195 uses a digital closed loop soft start system. The soft start ramp is generated internally by a
counter and digital-to-analog converter (DAC) that ramps up the effective reference voltage to the error amplifier.
The DAC supplies a voltage to the error amp that is used as the reference until that supplied voltage becomes
greater than the 591-mV reference voltage. At that point soft-start is complete and the 591-mV reference controls
the output voltage. The ramp rate is dependent on the oscillator frequency as each step in the DAC takes one
clock cycle from the oscillator. The user can choose from three ramp rates, or DAC counter widths depending on
viewpoint, for any given switching frequency by connecting the SS_SEL pin to GND, BP pin or letting the pin
float. The possibilities are summarized in Table 2.
Table 2. Soft Start Clock Cycles
SS_SEL Connection
Clock Cycles in 1-V Ramp (NDAC)
GND
2048
Floating
1024
BP
512
Copyright 2007–2008, Texas Instruments Incorporated
15
Product Folder Link(s): TPS40195
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