(
)
(
)
P P
OCLOS
OUT max
DS on
OCSET
I
R
V
2
R
2
I
-
-
-
÷
÷
÷
è
÷
è
=
÷
÷
÷
è
SLUSA30 – FEBRUARY 2010
www.ti.com
OCP sensing at LDRV is a true inductor valley current detection, using sample and hold.
Equation 2 can be used
to calculate ROCSET:
where
IOCSET is the internal current source
VOCLOS is the overall offset voltage
IP-P is the peak-to-peak inductor current
RDS(on) is the drain to source on-resistance of the low-side FET
IOUT(max) is the trip point for OCP
ROCSET is the resistor used for setting the OCP level
(2)
To avoid overcurrent tripping in normal operating load range, calculate ROCSET using the equation above with:
The maximum RDS(ON) at room temperature
The lower limit of VOCLOS (–8 mV) and the lower limit of IOCSET (9.5 A) from the Electrical Characteristics
table.
The peak-to-peak inductor current IP-P at minimum input voltage
Overcurrent is sensed across both the low-side FET and the high-side FET. If the voltage drop across either FET
exceeds the OC threshold, a count increments one count. If no OC is detected on either FET, the fault counter
decrements by one count. If three OC pulses are summed, a fault condition is declared which cycles the
soft-start function in a hiccup mode. Hiccup mode consists of four dummy soft-start timeouts followed by a real
one if overcurrent condition is encountered during normal operation, or five dummy soft-start timeouts followed
by a real one if overcurrent condition occurs from the beginning during start. This cycle continues indefinitely until
the fault condition is removed.
Drivers
The drivers for the external high-side and low-side MOSFETs are capable of driving a gate-to-source voltage of
VBP. The LDRV driver for the low-side MOSFET switches between BP and GND, while HDRV driver for the
high-side MOSFET is referenced to SW and switches between BOOT and SW. The drivers have
non-overlapping timing that is governed by an adaptive delay circuit to minimize body diode conduction in the
synchronous rectifier.
Pre-Bias Startup
The TPS40304A contains a circuit to prevent current from being pulled from the output during startup in the
condition the output is pre-biased. There are no PWM pulses until the internal soft-start voltage rises above the
error amplifier input (FB pin), if the output is pre-biased. Once the soft-start voltage exceeds the error amplifier
input, the controller slowly initiates synchronous rectification by starting the synchronous rectifier with a narrow
on time. It then increments that on time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D),
where D is the duty cycle of the converter. This approach prevents the sinking of current from a pre-biased
output, and ensures the output voltage startup and ramp to regulation is smooth and controlled.
12
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