=
SLEW
I
C
SR
=
SLEW
SS
SLEW
C
0.9 V
t
I
SLUSAD9 – DECEMBER 2010
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Light Load Power Saving Features
The TPS51461 has an automatic pulse-skipping mode to provide excellent efficiency over a wide load range.
The converter senses inductor current and prevents negative flow by shutting off the low-side gate driver. This
saves power by eliminating re-circulation of the inductor current. Further, when the bottom FET shuts off, the
converter enters discontinuous mode, and the switching frequency decreases, thus reducing switching losses as
well.
Voltage Slewing
The TPS51461 ramps the SLEW voltage up and down to perform the output voltage transitioning. The timing is
independent of switching frequency, as well as output resistive and capacitive loading. It is set by a capacitor
from SLEW pin to GND, called CSLEW, together with an internal current source of 10 A. The slew rate is used to
set the startup and voltage transition rate.
(4)
where
ISLEW = 10 A (nom)
SR is the target output voltage slew rate, per Intel specification between 0.5 mV/s and 10 mV/s
(5)
For the current reference design, an SR of 1 mV/s is targeted. The CSLEW is calculated to be 10 nF. The slower
slew rate is desired to minimize large inductor current perturbation during startup and voltage transitioning thus
reducing the possibility of acoustic noise.
After the power up, when VID1 is transitioning from 0 to 1, TPS51461 follows the SLEW voltage entering the
forced PWM mode to actively discharge the output voltage from 0.9 V to 0.8 V. The actual output voltage slew
rate is approximately the same as the set slew rate while the bandwidth of the converter supports it and there is
no overcurrent triggered by additional charging current flowing into the output capacitors. After SLEW transition is
completed, PWM mode is maintained for 64 s (16 clock cycles when the frequency is 1 MHz) to ensure voltage
regulation.
Protection Features
The TPS51461 offers many features to protect the converter power chain as well as the system electronics.
5-V Undervoltage Protection (UVLO)
The TPS51461 continuously monitors the voltage on the V5FILT pin to ensure that the voltage level is high
enough to bias the device properly and to provide sufficient gate drive potential to maintain high efficiency. The
converter starts with approximately 4.3 V and has a nominal of 440 mV of hysteresis. If the 5-V UVLO limit is
reached, the converter transitions the phase node into a 3-state function. And the converter remains in the off
state until the device is reset by cycling 5 V until the 5-V POR is reached (2.3-V nominal). The power input does
not have an UVLO function
Power Good Signals
The TPS51461 has one open-drain power good (PGOOD) pin. During startup, there is a 3 ms power good delay
starting from the output voltage reaching the regulation point (excluding soft-start ramp-up time). And there is
also a 1 ms power good high propagation delay. The PGOOD pin de-asserts as soon as the EN pin is pulled low
or an undervoltage condition on V5FILT is detected. The PGOOD signal is blanked during VID voltage transitions
to prevent false triggering during voltage slewing.
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