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参数资料
| 型号： | TPS54226PW |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 封装： | PACKAGE-14 |
| 文件页数： | 16/20页 |
| 文件大小： | 501K |
| 代理商： | TPS54226PW |
SW1
VBST
SS
V
O
VFB
GND
P
G
N
D
1
14
7
5
6
2
3
4
1
V
C
E
N
P
G
VREG5
13
12
11
9
8
P
G
N
D
2
10
SW2
V
IN
1
V
IN
2
16
15
SW3
EXPOSED
THERMAL
PAD
www.ti.com
SLVSA14B – OCTOBER 2009 – REVISED JUNE 2010
RGT PACKAGE
(TOP VIEW)
PIN FUNCTIONS
PIN
DESCRIPTION
NAME
PWP 14
RGT 16
VO
1
16
Connect to output of converter. This pin is used for On-Time Adjustment.
VFB
2
1
Converter feedback input. Connect with feedback resistor divider.
VREG5
3
2
5.5 V power supply output. A capacitor (typical 1mF) should be connected to GND.
SS
4
3
Soft-start control. A external capacitor should be connected to GND.
GND
5
4
Signal ground pin
PG
6
5
Open drain power good output
EN
7
6
Enable control input
PGND1,
Ground returns for low-side MOSFET. Also serve as inputs of current comparators. Connect PGND
8, 9
7, 8
PGND2
and GND strongly together near the IC.
Switch node connection between high-side NFET and low-side NFET. Also serve as inputs to current
SW1, SW2
10, 11
9, 10, 11
comparators.
Supply input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin to
VBST
12
respective SW1, SW2 terminals. An internal PN diode is connected between VREG5 to VBST pin.
VIN
13
13, 14
Power input and connected to high side NFET drain
VCC
14
15
Supply input for 5 V internal linear regulator for the control circuitry
Exposed
Thermal
Back
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Should be
Pad or
side
connected to PGND.
PowerPAD
Copyright 2009–2010, Texas Instruments Incorporated
5
Product Folder Link(s): TPS54226
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