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| 型号： | TPS54226RGTT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | DUAL SWITCHING CONTROLLER, PQCC16 |
| 封装： | GREEN, PLASTIC, QFN-16 |
| 文件页数： | 12/27页 |
| 文件大小： | 923K |
| 代理商： | TPS54226RGTT |
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SLVSA14D
– OCTOBER 2009 – REVISED FEBRUARY 2011
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
TRANSPORT
TA
PACKAGE(2) (3)
ORDERABLE PART NUMBER
PIN
MEDIA
TPS54226PWP
Tube
PowerPAD
14
(HTSSOP)
– PWP
TPS54226PWPR
Tape and Reel
–40°C to 85°C
TPS54226RGTT
Tape and Reel
Plastic Quad Flat Pack (QFN)
16
TPS54226RGTR
Tape and Reel
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2)
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3)
All package options have Cu NIPDAU lead/ball finish.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
VIN, VCC, EN
–0.3 to 20
V
VBST
–0.3 to 26
V
VBST (vs SW1, SW2)
–0.3 to 6.5
V
VI
Input voltage range
VFB, VO, SS, PG
–0.3 to 6.5
V
SW1, SW2
–2 to 20
V
SW1, SW2 (10 ns transient)
–3 to 20
V
VREG5
–0.3 to 6.5
V
VO
Output voltage range
PGND1, PGND2
–0.3 to 0.3
V
IO
Output current range
IVREG5
Vdiff
Voltage from GND to POWERPAD
–0.2 to 0.2
V
Human Body Model (HBM)
2
kV
Electrostatic
ESD rating
discharge
Charged Device Model (CDM)
500
V
TJ
Operating junction temperature
–40 to 150
°C
Tstg
Storage temperature
–55 to 150
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
TPS54226
THERMAL METRIC(1)
PWP
RGT
UNITS
14 PINS
16 PINS
θJA
Junction-to-ambient thermal resistance
55.6
46.1
θJCtop
Junction-to-case (top) thermal resistance
51.3
58.1
θJB
Junction-to-board thermal resistance
26.4
18.8
°C/W
ψJT
Junction-to-top characterization parameter
1.8
1.3
ψJB
Junction-to-board characterization parameter
20.6
18.8
θJCbot
Junction-to-case (bottom) thermal resistance(2)
4.3
4.8
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
2
2009–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS54226
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