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| 型号： | TPS54260DGQR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING REGULATOR, 2500 kHz SWITCHING FREQ-MAX, PDSO10 |
| 封装： | GREEN, PLASTIC, MSOP-10 |
| 文件页数： | 15/49页 |
| 文件大小： | 1808K |
| 代理商： | TPS54260DGQR |
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RT/CLK
TPS54260
Clock
Source
PLL
Rfset
10pF
4kW
50 W
EXT
SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010
www.ti.com
DETAILED DESCRIPTION (continued)
How to Interface to RT/CLK Pin
The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the
synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in
Figure 41. The square wave amplitude must transition lower than 0.5V and higher than 2.2V on the RT/CLK pin
and have an on time greater than 40 ns and an off time greater than 40 ns. The synchronization frequency range
is 300 kHz to 2200 kHz. The rising edge of the PH will be synchronized to the falling edge of RT/CLK pin signal.
The external synchronization circuit should be designed in such a way that the device will have the default
frequency set resistor connected from the RT/CLK pin to ground should the synchronization signal turn off. It is
recommended to use a frequency set resistor connected as shown in Figure 41 through a 50
resistor to
ground. The resistor should set the switching frequency close to the external CLK frequency. It is recommended
to ac couple the synchronization signal through a 10 pF ceramic capacitor to RT/CLK pin and a 4k
series
resistor. The series resistor reduces PH jitter in heavy load applications when synchronizing to an external clock
and in applications which transition from synchronizing to RT mode. The first time the CLK is pulled above the
CLK threshold the device switches from the RT resistor frequency to PLL mode. The internal 0.5V voltage source
is removed and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal. Since
there is a PLL on the regulator the switching frequency can be higher or lower than the frequency set with the
external resistor. The device transitions from the resistor mode to the PLL mode and then will increase or
decrease the switching frequency until the PLL locks onto the CLK frequency within 100 microseconds.
When the device transitions from the PLL to resistor mode the switching frequency will slow down from the CLK
frequency to 150 kHz, then reapply the 0.5V voltage and the resistor will then set the switching frequency. The
switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSE pin. The
device implements a digital frequency shift to enable synchronizing to an external clock during normal startup
and fault conditions. Figure 42, Figure 43 and Figure 44 show the device synchronized to an external system
clock in continuous conduction mode (ccm) discontinuous conduction (dcm) and pulse skip mode (psm).
Figure 41. Synchronizing to a System Clock
22
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS54260
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| TPS54260MDRCTEP | 功能描述:IC REG BUCK ADJ 2.5A 10VSON 制造商:texas instruments 系列:Eco-Mode? 包装:剪切带（CT） 零件状态:在售 功能:降压 输出配置:正 拓扑:降压 输出类型:可调式 输出数:1 电压 - 输入（最小值）:3.5V 电压 - 输入（最大值）:60V 电压 - 输出（最小值/固定）:0.8V 电压 - 输出（最大值）:60V 电流 - 输出:2.5A 频率 - 开关:100kHz ~ 2.5MHz 同步整流器:无 工作温度:-40°C ~ 150°C（TJ） 安装类型:表面贴装 封装/外壳:10-VFDFN 裸露焊盘 供应商器件封装:10-VSON（3x3） 标准包装:1 |
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