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参数资料
| 型号： | TPS5431DDA |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 6 A SWITCHING REGULATOR, 600 kHz SWITCHING FREQ-MAX, PDSO8 |
| 封装： | GREEN, PLASTIC, SOP-8 |
| 文件页数： | 9/28页 |
| 文件大小： | 810K |
| 代理商： | TPS5431DDA |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页
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Fp1=500000x
VO
FLC
(15)
Fz1=0.7xF
LC
(16)
Fz2=2.5xF
LC
(17)
C7=
1
2
xFp1x(R1||R2)
p
(18)
R3=
1
2
xFz1xC7
p
(19)
C6=
1
2
xFz2xR1
p
(20)
ADVANCED INFORMATION
Output Voltage Limitations
V
OUTMAX + 0.87
V
INMIN * IOMAX
0.230 ) VD * IOMAX
R
L * VD
(21)
V
OUTMIN + 0.12
V
INMAX * IOMIN
0.110 ) VD * IOMIN
R
L * VD
(22)
SLVS632C – JANUARY 2006 – REVISED NOVEMBER 2006
The final pole is located at a frequency too high to be of concern. The second zero, Fz2 as defined by
Equation 17 uses 2.5 for the frequency multiplier. In some cases this may need to be slightly higher or lower.
Values in the range of 2.3 to 2.7 work well. The values for R1 and R2 are fixed by the 3.3-V output voltage as
calculated usingEquation 12. For this design R1 = 10 k
and R2 = 5.90 k. With Fp1 = 401 Hz, Fz1 = 2876 Hz
and Fz2 = 10.3 kHz, the values of R3, C6 and C7 are determined using Equation 18, Equation 19, and
For this design, using the closest standard values, C7 is 0.1
F, R3 is 549 , and C6 is 1500 pF. C4 is added to
improve load regulation performance. It is effectively in parallel with C6 in the location of the second pole
frequency, so it should be small in relationship to C6. C4 should be less the 1/10 the value of C6. For this
example, 150 pF works well.
For additional information on external compensation of the TPS5430, TPS5431 or other wide voltage range
SWIFT devices, see SLVA237 Using TPS5410/20/30/31 With Aluminum/Ceramic Output Capacitors
Due to the internal design of the TPS5430, there are both upper and lower output voltage limits for any given
input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87%
and is given by:
Where
VINMIN = minimum input voltage
IOMAX = maximum load current
VD = catch diode forward voltage.
RL= output inductor series resistance.
This equation assumes maximum on resistance for the internal high side FET.
The lower limit is constrained by the minimum controllable on time which may be as high as 200 ns. The
approximate minimum output voltage for a given input voltage and minimum load current is given by:
Where
VINMAX = maximum input voltage
IOMIN = minimum load current
VD = catch diode forward voltage.
RL= output inductor series resistance.
This equation assumes nominal on resistance for the high side FET and accounts for worst case variation of
operating frequency set point. Any design operating near the operational limits of the device should be
carefully checked to assure proper functionality.
17
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