TPS54352,TPS54353
TPS54354,TPS54355
TPS54356,TPS54357
SLVS519A MAY 2004 REVISED OCTOBER 2004
www.ti.com
20
Where K is the frequency multiplier for the spread between
fLC and fCO. K should be between 5 and 15, typically 10 for
one decade difference. For a desired crossover of 20 kHz
and a 22-
H inductor, the minimum value for the output
capacitor is 288
F. The selected output capacitor must be
rated for a voltage greater than the desired output voltage
plus one half the ripple voltage. Any derating amount must
also be included. The maximum RMS ripple current in the
output capacitor is given by equation 16:
I
COUT(RMS) +
1
12
V
OUT
V
IN(MAX) *
V
OUT
V
IN(MAX)
L
OUT
sw
(16)
The calculated RMS ripple current is 156 mA in the
output capacitors.
CHOOSING CAPACITOR VALUE
For this design example, a relatively large aluminum
electrolytic capacitor is combined with a smaller value
ceramic capacitor. This combination provides a stable high
performance design at a relatively low cost. Also, by
carefully choosing the capacitor values and ESRs, the
design can be tailored to complement the internal
compensation poles and zeros of the TPS54356.
These preconfigured poles and zeroes internal to the
TPS54356 limit the range of output filter configurations. A
variety of capacitor values and types of dielectric are
supported. There are a number of different ways to
calculate the output filter capacitor value and ESR to work
with the internal compensation network. This procedure
outlines a relatively simple procedure that produces good
results with an output filter consisting of a high ESR
dielectric capacitor in parallel with a low ESR ceramic
capacitor. Use of the SWIFT Designer Software for
designs with unusually high closed loop crossover
frequencies, low value, low ESR output capacitors such as
ceramics or if the designer is unsure about the design
procedure.
The TPS54356 contains a compensation network with the
following nominal characteristics:
INT +
1.7 kHZ
Z1 +
2.5 kHZ
Z2 +
4.8 kHZ
P1 +
95 kHZ
P2 +
125 kHZ
For a stable design, the closed loop crossover frequency
should be set less than one fifth of the switching frequency,
and the phase margin at crossover must be greater than
45 degrees. The general procedure outlined here
produces results consistent with these requirements
without going into great detail about the theory of loop
compensation.
In this case, the output filter LC corner frequency should be
selected to be near the first compensation zero frequency
as described by equation 17:
LC +
1
2
p L
OUT
C2
^
Z1
Placement of the LC corner frequency at fZ1 is not critical,
it only needs to be close. For the design example, fLC = 2
kHz.
Solving for C2 using equation 18:
C2
^
1
4
p22
Z1
L
OUT
The desired value for C2 is calculated as 184
F. A close
standard value of 330
F is chosen with a resulting LC
corner frequency of 1.9 kHz. As to be shown, this value is
not critical as long as it results in a corner frequency in the
vicinity of fZ1.
Next, when using a large ceramic capacitor in parallel with
a high ESR electrolytic capacitor, there is a pole in the
output filter that should be at fZ2 as shown in equation 19:
P(ESR) +
1
2
pR
(C2ESR)
C5
+
Z2
Now the actual C2 capacitor must be selected based on
the ESR and the value of capacitor C5 so that the above
equation is satisfied. In this example, the R(C2ESR)C5
product should be 3.18
105. From the available
capacitors, by choosing a Panasonic EEVFKOJ331XP
aluminum electrolytic capacitor with a nominal ESR of
0.34
yields a calculated value for C5 of 98 F. The
closest standard value is 100
F. As the actual ESR of the
capacitor can vary by a large amount, this value also is not
critical.
The closed loop crossover frequency should be greater
than fLC and less than one fifth of the switching frequency.
Also, the crossover frequency should not exceed 70 kHz,
as the error amplifier may not provide the desired gain. As
stated previously, closed loop crossover frequencies
between 5 and 15 times fLC work well. For this design, the
crossover frequency can be estimated by:
CO +
1.125
10*
3
P(ESR)
LC
This simplified equation is valid for this design because the
output filter capacitors are mixed technology. Compare
this result to the actual measured loop response plot of
(17)
(18)
(19)
(20)