SLVSAD6B – AUGUST 2010 – REVISED NOVEMBER 2010
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Power Good
The TPS54426 has power-good open drain output. The power good function is activated after soft start has
finished. The power good function becomes active after 1.7 times soft-start time. When the output voltage is
within -10% of the target value, internal comparators detect power good state and the power good signal
becomes high. Rpg resister value ,which is connected between PG and VREG5, is required from 20k
Ω to 150kΩ.
If the feedback voltage goes under 15% of the target value, the power good signal becomes low after a 5 ms
internal delay.
VREG5
VREG5 is an internally generated voltage source used by the TPS54425. It is derived directly from the input
voltage and is nominally regulated to 5.5 V when the input voltage is above 5.6 V. The output of the VREG5
regulator is the input to the internal UVLO function. VREG5 must be above the UVLO wake up threshold voltage
(3.8 V typical) for the TPS54425 to function. Connect a 1.0 F capacitor between pin 3 of the TPS54425 and
power ground for proper regulation of the VREG5 output. The VREG5 output voltage is available for external use
and can typically source up to 70 mA. The VREG5 output is disabled when the TPS54425 EN pin is open or
pulled low.
Output Discharge Control
TPS54426 discharges the output when EN is low, or the controller is turned off by the protection functions (OVP,
UVP, UVLO and thermal shutdown). The output is discharged by an internal 50-
MOSFET which is connected
from VO to PGND. The internal low-side MOSFET is not turned on during the output discharge operation to
avoid the possibility of causing negative voltage at the output.
Current Protection
The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time, and the output inductor value. During the on-time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. If the measured voltage is
above the voltage proportional to the current limit. Then, the device constantly monitors the low-side FET switch
voltage, which is proportional to the switch current, during the low-side on-time.
The converter maintains the low-side switch on until the measured voltage is below the voltage corresponding to
the current limit at which time the switching cycle is terminated and a new switching cycle begins. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of overcurrent protection. The load current one half of the
peak-to-peak inductor current higher than the overcurrent threshold. Also when the current is being limited, the
output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. This may cause the output under-voltage protection circuit to be activated. When the overcurrent
condition is removed, the output voltage will return to the regulated value. This protection is non-latching.
Over/Under Voltage Protection
TPS54426 monitors a resistor divided feedback voltage to detect over and under voltage. When the feedback
voltage becomes higher than 120% of the target voltage, the OVP comparator output goes high and the circuit
latches as the high-side MOSFET driver turns off and the low-side MOSFET turns on. When the feedback
voltage becomes lower than 65% of the target voltage, the UVP comparator output goes high and an internal
UVP delay counter begins. After 250 ms, the device latches off both internal top and bottom MOSFET. This
function is enabled approximately 1.7 x softstart time.
UVLO Protection
Undervoltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower
than UVLO threshold voltage, the TPS54426 is shut off. This is protection is non-latching.
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