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参数资料
| 型号： | TPS5450MDDAREP |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 11.7 A SWITCHING REGULATOR, 600 kHz SWITCHING FREQ-MAX, PDSO8 |
| 封装： | GREEN, PLASTIC, SOIC-8 |
| 文件页数： | 23/24页 |
| 文件大小： | 772K |
| 代理商： | TPS5450MDDAREP |
Undervoltage Lockout (UVLO)
Boost Capacitor (BOOT)
Output Feedback (VSENSE) and Internal Compensation
Voltage Feed Forward
Feed Forward Gain +
VIN
Ramp
pk*pk
(1)
Pulse-Width-Modulation (PWM) Control
Overcurrent Limiting
SLVS935 – JULY 2009 ....................................................................................................................................................................................................... www.ti.com
The ENA pin has an internal pullup current source, allowing the user to float the ENA pin. If an application
requires controlling the ENA pin, use open drain or open collector output logic to interface with the pin. To limit
the start-up inrush current, an internal slow-start circuit is used to ramp up the reference voltage from 0 V to its
final value, linearly. The internal slow start time is 8 ms (typical).
The TPS5450 incorporates an undervoltage lockout circuit to keep the device disabled when VIN (the input
voltage) is below the UVLO start voltage threshold. During power up, internal circuits are held inactive and the
internal slow start is grounded until VIN exceeds the UVLO start threshold voltage. Once the UVLO start
threshold voltage is reached, the internal slow start is released and device start-up begins. The device operates
until VIN falls below the UVLO stop threshold voltage. The typical hysteresis in the UVLO comparator is 330 mV.
Connect a 0.01-
F low-ESR ceramic capacitor between the BOOT pin and PH pin. This capacitor provides the
gate drive voltage for the high-side MOSFET. X7R or X5R grade dielectrics are recommended due to their stable
values over temperature.
The output voltage of the regulator is set by feeding back the center point voltage of an external resistor divider
network to the VSENSE pin. In steady-state operation, the VSENSE pin voltage should be equal to the voltage
reference 1.221 V.
The TPS5450 implements internal compensation to simplify the regulator design. Because the TPS5450 uses
voltage-mode control, a type 3 compensation network has been designed on chip to provide a high crossover
frequency and a high phase margin for good stability. See the Internal Compensation Network section for more
details.
The internal voltage feed forward provides a constant dc power stage gain despite any variations with the input
voltage. This greatly simplifies the stability analysis and improves the transient response. Voltage feed forward
varies the peak ramp voltage inversely with the input voltage so that the modulator and power stage gain are
constant at the feed forward gain:
The typical feed forward gain of TPS5450 is 25.
The regulator employs a fixed frequency pulse-width-modulator (PWM) control method. First, the feedback
voltage (VSENSE pin voltage) is compared to the constant voltage reference by the high-gain error amplifier and
compensation network to produce a error voltage. Then, the error voltage is compared to the ramp voltage by the
PWM comparator. In this way, the error-voltage magnitude is converted to a pulse width, which is the duty cycle.
Finally, the PWM output is fed into the gate drive circuit to control the on-time of the high-side MOSFET.
Overcurrent limiting is implemented by sensing the drain-to-source voltage across the high-side MOSFET. The
drain to source voltage is then compared to a voltage level representing the overcurrent threshold limit. If the
drain-to-source voltage exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The system
ignores the overcurrent indicator for the leading edge blanking time at the beginning of each cycle to avoid any
turn-on noise glitches.
Once overcurrent indicator is set true, overcurrent limiting is triggered. The high-side MOSFET is turned off for
the rest of the cycle after a propagation delay. The overcurrent limiting mode is called cycle-by-cycle current
limiting.
8
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS5450-EP
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