参数资料
型号: TPS54550PWP
厂商: Texas Instruments
文件页数: 16/31页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 6A 16HTSSOP
产品培训模块: Understanding SWIFT Step Down Dc/Dc Converters
标准包装: 90
系列: SWIFT™
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.9 V ~ 12 V
输入电压: 4.5 V ~ 20 V
频率 - 开关: 250kHz,500kHz
电流 - 输出: 6A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 管件
供应商设备封装: 16-HTSSOP
产品目录页面: 1029 (CN2011-ZH PDF)
配用: 296-19743-ND - EVALUATION MODULE FOR TPS54550
其它名称: 296-19672-5

SLVS623A – MARCH 2006 – REVISED APRIL 2006
APPLICATION INFORMATION
www.ti.com
Vin
INPUT
BULK
FILTER
TOPSIDE GROUND AREA
INPUT
BYPASS
CAPACITOR
BOOT
CAPACITOR
AND
RESISTOR
LOW
SIDE
FET
OUTPUT
FILTER
CAPACITOR
UNDER VOLTAGE
LOCK OUT
RESISTOR DIVIDER
VIN
VIN
UVLO
BOOT
PH
PH
PH
VOUT
3.3 OR 5 V
POWER GOOD PULLUP
PWRGD
EXPOSED
POWERPAD
LSG
OUTPUT INDUCTOR
RT
AREA
VBIAS
BIAS
CAPACITOR
SLOW START
CAPACITOR
SYNC
SS/ENA
COMP
PGND
AGND
VSENSE
COMPENSATION NETWORK
ANALOG GROUND TRACE
VIA
BACKSIDE or INTERNAL
LAYER TRACE
Figure 26. TPS54550 PCB Layout
PCB LAYOUT
The VIN pins should be connected together on the
printed circuit board (PCB) and bypassed with a low
ESR ceramic bypass capacitor. Care should be
taken to minimize the loop area formed by the
bypass capacitor connections, the VIN pins, and
source of the low-side MOSFET. The minimum
recommended bypass capacitance is 10- μ F ceramic
with a X5R or X7R dielectric and the optimum
placement is closest to the VIN pins and the source
of the low-side MOSFET. See Figure 26 for a PCB
layout example. The AGND and PGND pins should
be tied to the PCB ground plane at the pins of the IC.
The source of the low-side MOSFET should be
connected directly to the PCB ground plane. The PH
pins should be tied together and routed to the drain
of the low-side MOSFET. Since the PH connection is
the switching node, the MOSFET should be located
very close to the PH pins, and the area of the PCB
conductor minimized to prevent excessive capacitive
coupling. The recommended conductor width from
pins 14 and 15 is 0.050 inch to 0.075 inch of 1-ounce
to 2-ounce copper. The length of the copper land
pattern should be no more than 0.2 inch.
For operation at full rated load, the analog ground
plane must provide adequate heat dissipating area.
A 3-inch by 3-inch plane of copper is recommended,
though not mandatory, depending on ambient
temperature and airflow. Most applications have
larger areas of internal ground plane available, and
the PowerPAD should be connected to the largest
area available. Additional areas on the bottom or top
layers also help dissipate heat, and any area
available should be used when 5 A or greater
operation is desired. Connection from the exposed
area of the PowerPAD to the analog ground plane
layer should be made using 0.013-inch diameter vias
to avoid solder wicking through the vias. Four vias
should be in the PowerPAD area with four additional
vias outside the pad area and underneath the
package. Additional vias beyond those
recommended to enhance thermal performance
should be included in areas not under the device
package. See Figure 27.
16
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