参数资料
型号: TPS60110PWPRG4
厂商: Texas Instruments
文件页数: 2/26页
文件大小: 0K
描述: IC REG BST SWITCHED CAP 20HTSSOP
标准包装: 2,000
类型: 升压(升压),切换电容(充电泵)
输出类型: 固定
输出数: 1
输出电压: 5V
输入电压: 2.7 V ~ 5.4 V
频率 - 开关: 300kHz
电流 - 输出: 300mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 20-HTSSOP
配用: 296-10946-ND - EVAL MOD FOR TPS60110
TPS60110
REGULATED 5 V 300 mA LOW NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS215C ? JUNE 1999 ? REVISED AUGUST 2008
PWP PACKAGE
(TOP VIEW)
GND
SYNC
1
2
20
19
GND
CLK
ENABLE
FB
OUT
C1+
IN
C1?
PGND
PGND
3
4
5
6
7
8
9
10
18
17
16
15
14
13
12
11
COM
SKIP
OUT
C2+
IN
C2?
PGND
PGND
Thermal
Pad
Figure 2. Bottom View of PWP Package,
Showing the Thermal Pad
AVAILABLE OPTIONS
PACKAGE
TSSOP?
(PWP)
TPS60110PWP
? This package is available taped and reeled. To order this packaging
option, add an R suffix to the part number (e.g., TPS60110PWPR).
Terminal Functions
TERMINAL
NAME
CLK
C1+
C1?
C2+
C2?
COM
NO.
19
6
8
15
13
18
I/O
I
I
DESCRIPTION
Input for external clock signal. If the internal clock is used, connect this terminal to GND.
Positive terminal of the charge-pump capacitor C1F
Negative terminal of the charge-pump capacitor C1F
Positive terminal of the charge-pump capacitor C2F
Negative terminal of the charge-pump capacitor C2F
Mode selection.
When COM is logic low the charge pump operates in push-pull mode to minimize output ripple. When COM is
connected to IN the regulator operates in single-ended mode requiring only one flying capacitor.
ENABLE
3
I
ENABLE Input. The device turns off, the output disconnects from the input, and the supply current decreases
to 0.05 μ A when ENABLE is a logic low. ENABLE High may only be applied when VIN is inside the recommended
operating range.
FB
4
I
FEEDBACK input. Connect FB to OUT as close to the load as possible to achieve best regulation. Resistive
divider is on-chip to match internal reference voltage of 1.22 V.
GND
1, 20
GROUND. Analog ground for internal reference and control circuitry. Connect to PGND through a short trace.
IN
7, 14
I
Supply Input. Connect to an input supply in the 2.7-V to 5.4-V range. Bypass IN to GND with a (CO/2) μ F
capacitor. Connect both INs through a short trace.
OUT
5, 16
O
Regulated 5-V power output. Connect both OUTs through a short trace and bypass OUT to GND with the output
filter capacitor CO.
PGND
9?12
PGND power ground. Charge-pump current flows through this pin. Connect all PGNDs together.
SKIP
17
I
Mode selection. When SKIP is logic low, the charge pump operates in constant-frequency mode. Output ripple
and noise are minimized in this mode. When SKIP is connect to IN, the device operates in pulse skip mode.
Quiescent current is lowest in this mode.
SYNC
2
I
Selection for external clock signal. Connect to GND to use the internally generated clock signal. Connect to IN
for external synchronization. In this case, the clock signal needs to be fed through CLK.
PowerPAD ?
Must be soldered to achieve appropriate power dissipation. Should be connected to PGND.
2
POST OFFICE BOX 655303
? DALLAS, TEXAS 75265
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