参数资料
型号: TPS60250RTE
厂商: TEXAS INSTRUMENTS INC
元件分类: 稳压器
英文描述: 0.65 A SWITCHED CAPACITOR CONVERTER, 750 kHz SWITCHING FREQ-MAX, PQCC16
封装: 3 X 3 MM, PLASTIC, QFN-16
文件页数: 4/25页
文件大小: 762K
代理商: TPS60250RTE
SERIAL INTERFACE
Dataline
stable;
datavalid
DATA
CLK
Change
ofdata
allowed
STARTCondition
DATA
CLK
STOP Condition
S
P
CE
SLVS769C – APRIL 2007 – REVISED APRIL 2008............................................................................................................................................................ www.ti.com
applications. In order to satisfy today's requirements on LED current , the TPS60250/2 cover the low LED current
area from 100
A to 1.5 mA with 100 A dimming steps (total 16 steps for a 25 mA maximum current) for the
new LCD panels which have improved transparency rates. For LED currents in the range from 2 mA to 25 mA,
the devices use 48 dimming steps with 0.5 mA steps. Also, DM5 has 4 dimming steps once the current path is
assigned for auxiliary applications with a 80 mA maximum current.
The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to
400 kHz. The interface adds flexibility to the WLED driver solution, enabling most functions to be programmed to
new values depending on the instantaneous application requirements. Register contents remain intact as long as
VCC remains above UVLO2 (typical 1.3 V).
For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are
reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable
whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start
condition and terminated with a stop condition. When addressed, the TPS60250/2 devices generate an
acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra
clock pulse that is associated with the acknowledge bit. The TPS60250/2 devices must pull down the DATA line
during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the
acknowledge clock pulse. Setup and hold times must be taken into account. During read operations, a master
must signal the end of data to the slave by not generating an acknowledge bit on the last byte that was clocked
out of the slave. In this case, the slave TPS60250/2 devices must leave the data line high to enable the master
to generate the stop condition.
Figure 15. Bit Transfer on the Serial Interface
Figure 16. START and STOP Conditions
12
Copyright 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS60250 TPS60252
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TPS60250RTER 功能描述:LED照明驱动器 High Eff Charge Pump RoHS:否 制造商:STMicroelectronics 输入电压:11.5 V to 23 V 工作频率: 最大电源电流:1.7 mA 输出电流: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:SO-16N
TPS60250RTERG4 功能描述:LED照明驱动器 High Eff Charge Pump RoHS:否 制造商:STMicroelectronics 输入电压:11.5 V to 23 V 工作频率: 最大电源电流:1.7 mA 输出电流: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:SO-16N
TPS60250RTET 功能描述:LED照明驱动器 High Eff Charge Pump RoHS:否 制造商:STMicroelectronics 输入电压:11.5 V to 23 V 工作频率: 最大电源电流:1.7 mA 输出电流: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:SO-16N
TPS60250RTET 制造商:Texas Instruments 功能描述:DC/DC Charge Pump Converter IC
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