参数资料
型号: TPS61106PWRG4
厂商: TEXAS INSTRUMENTS INC
元件分类: 稳压器
英文描述: 1.8 A SWITCHING REGULATOR, 800 kHz SWITCHING FREQ-MAX, PDSO20
封装: GREEN, PLASTIC, TSSOP-20
文件页数: 14/34页
文件大小: 798K
代理商: TPS61106PWRG4
www.ti.com
DVESR + IOUT
R
ESR
(8)
Output Capacitor LDO
LAYOUT CONSIDERATIONS
APPLICATION EXAMPLES
SWN
C3
10
F
L1
10
H
R1
R2
VBAT
VOUT
LDOIN
LDOSENSE
LDOOUT
R7
R8
R9
C6
2.2
F
C4
100
F
U1
LBO1
LBO2
PGOOD
PGND
LBI
SKIPEN
ADEN
EN
ENPB
LDOEN
GND
TPS61106
List of Components:
U1 = TPS61106
L1 = SUMIDA CDRH74–100
C3, C5, C6 = X7R/X5R Ceramic
C4 = Low ESR Tantalum
3.3 V,
>250 mA
C5
2.2
F
1.5 V,
>120 mA
LBO1
LBO2
PGOOD
TPS61100, TPS61103
TPS61106, TPS61107
SLVS411B – JUNE 2002 – REVISED APRIL 2004
With a chosen ripple voltage of 15 mV, a minimum capacitance of 10 F is needed. The total ripple is larger due
to the ESR of the output capacitor. This additional component of the ripple can be calculated using Equation 8:
An additional ripple of 10 mV is the result of using a tantalum capacitor with a low ESR of 100 m
. The total
ripple is the sum of the ripple caused by the capacitance and the ripple caused by the ESR of the capacitor. In
this example, the total ripple is 25 mV. It is possible to improve the design by enlarging the capacitor or using
smaller capacitors in parallel to reduce the ESR or by using better capacitors with lower ESR, like ceramics. So,
trade-offs have to be made between performance and costs of the converter circuit.
To ensure stable output regulation, it is required to use an output capacitor at the LDO output. We recommend
using ceramic capacitors in the range from 1 F up to 4.7 F. At 4.7 F and above it is recommended to use
standard ESR tantalum. There is no maximum capacitance value.
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC.
Use a common ground node for power ground and a different one for control ground to minimize the effects of
ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC.
The feedback divider should be placed as close as possible to the control ground pin of the IC. To lay out the
control ground, it is recommended to use short traces as well, separated from the power ground traces. This
avoids ground shift problems, which can occur due to superimposition of power ground current and control
ground current.
Figure 29. Solution for Maximum Output Power
21
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