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参数资料
| 型号： | TPS62063DSGT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 1.6 A SWITCHING REGULATOR, 3400 kHz SWITCHING FREQ-MAX, PDSO8 |
| 封装： | 2 X 2 MM, 0.75 MM HEIGHT, GREEN, PLASTIC, WSON-8 |
| 文件页数： | 5/26页 |
| 文件大小： | 1109K |
| 代理商： | TPS62063DSGT |
Outputvoltage
Vout (PWM)
Vout +1%
PFMComparator
threshold
VoltagePositioning
Lightload
PFMMode
moderatetoheavyload
PWMMode
SLVSA95A
– MARCH 2010 – REVISED JANUARY 2011
Figure 22. Power Save Mode Operation with automatic Mode transition
100% Duty Cycle Low Dropout Operation
The device starts to enter 100% duty cycle mode as the input voltage comes close to the nominal output voltage.
In order to maintain the output voltage, the High-Side MOSFET switch is turned on 100% for one or more cycles.
With further decreasing VIN the High-Side MOSFET switch is turned on completely. In this case the converter
offers a low input-to-output voltage difference. This is particularly useful in battery-powered applications to
achieve longest operation time by taking full advantage of the whole battery voltage range.
The minimum input voltage to maintain regulation depends on the load current and output voltage, and can be
calculated as:
VINmin = VOmax + IOmax × (RDS(on)max + RL)
With:
IOmax = maximum output current
RDS(on)max = maximum P-channel switch RDS(on).
RL = DC resistance of the inductor
VOmax = nominal output voltage plus maximum output voltage tolerance
Undervoltage Lockout
The under voltage lockout circuit prevents the device from malfunctioning at low input voltages and from
excessive discharge of the battery. It disables the output stage of the converter once the falling VIN trips the
under-voltage lockout threshold VUVLO. The under-voltage lockout threshold VUVLO for falling VIN is typically
1.78V. The device starts operation once the rising VIN trips under-voltage lockout threshold VUVLO again at
typically 1.95V.
Output Capacitor Discharge.
With EN = GND, the devices enter shutdown mode and all internal circuits are disabled. The SW pin is
connected to PGND via an internal resistor to discharge the output capacitor.
MODE SELECTION
The MODE pin allows mode selection between forced PWM mode and Power Save Mode.
Connecting this pin to GND enables the Power Save Mode with automatic transition between PWM and PFM
mode. Pulling the MODE pin high forces the converter to operate in fixed frequency PWM mode even at light
load currents. This allows simple filtering of the switching frequency for noise sensitive applications. In this mode,
the efficiency is lower compared to the power save mode during light loads.
2010–2011, Texas Instruments Incorporated
13
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