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参数资料
| 型号： | TPS62112MRSATEP |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 2.4 A SWITCHING REGULATOR, 1100 kHz SWITCHING FREQ-MAX, PQCC16 |
| 封装： | PLASTIC, QFN-16 |
| 文件页数： | 22/25页 |
| 文件大小： | 786K |
| 代理商： | TPS62112MRSATEP |
www.ti.com
DEVICE INFORMATION
PIN ASSIGNMENT TOP VIEW
16 15 14 13
5
6
7
8
1
2
3
4
9
GND
FB
AGND
PGND
Exposed
Thermal
Pad
VIN
EN
PGND
SW
LBI
VINA
SW
PG
SYNC
LBO
12
11
10
SLVS630B – APRIL 2007 – REVISED OCTOBER 2007
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Enable. A logic high enables the converter; logic low forces the device into shutdown mode reducing the
EN
4
I
supply current to less than 2 A.
Feedback pin for the fixed output voltage option. For the adjustable version, an external resistive divider
FB
10
I
is connected to this pin. The internal voltage divider is disabled for the adjustable version.
LBO
6
O
Open-drain, low-battery output. This pin is pulled low if LBI is below its threshold.
GND
11, 12
I
Ground
LBI
7
I
Low-battery input
Connect the inductor to this pin. This pin is the switch pin and connected to the drain of the internal
SW
14, 15
O
power MOSFETS.
Power good comparator output. This is an open-drain output. A pullup resistor should be connected
PG
13
O
between PG and VOUT. The output goes active high when the output voltage is greater than 98.4% of
the nominal value.
PGND
1, 16
I
Power ground. Connect all power grounds to this pin.
AGND
9
I
Analog ground, connect to GND and PGND
Input for synchronization to external clock signal. Synchronizes the converter switching frequency to an
external clock signal with CMOS level:
SYNC
5
I
SYNC = HIGH: Low-noise mode enabled, fixed frequency PWM operation is forced
SYNC = LOW (GND): Power save mode enabled, PFM/PWM mode enabled
VIN
2, 3
I
Supply voltage input (power stage)
VINA
8
I
Supply voltage input (support circuits)
PowerPAD
Connect to AGND
6
Copyright 2007, Texas Instruments Incorporated
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