Output Capacitor Selection
DVO +
V
O
V
I
V
I *
V
O
L
sw
1
8
C
O
sw )
ESR
, maximum for high V
I
(3)
Input Capacitor Selection
Checking Loop Stability
www.ti.com .............................................................................................................................................................. SLVS540E – MAY 2006 – REVISED APRIL 2008
Table 5. List of Inductors
MANUFACTURER
SERIES
DIMENSIONS
FDK
MIPSA2520
2.5
× 2.0 × 1.2 = 6 mm3
TDK
VLF3010AT
2.8
× 2.6 × 1 = 7.28 mm3
LPS3010
3
× 3 × 1 = 9 mm3
Coilcraft
LPS3015
3
× 3 × 1.5 = 13.5 mm3
The advanced fast-response voltage mode control scheme of the TPS6235x allows the use of tiny ceramic
capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are
recommended. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors,
aside from their wide variation in capacitance overtemperature, become resistive at high frequencies.
At nominal load current, the device operates in PWM mode and the overall output voltage ripple is the sum of the
voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the
output capacitor:
At light loads, the device operates in power-save mode and the output voltage ripple is independent of the output
capacitor value. The output voltage ripple is set by the internal comparator thresholds and propagation delays.
The typical output voltage ripple is 2% of the nominal output voltage VO.
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required to prevent large voltage transients that can cause misbehavior of the device or interferences with other
circuits in the system. For most applications, a 10-
F capacitor is sufficient.
Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce
ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even
damage the part.
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
Switching node, SW
Inductor current, I
L
Output ripple voltage, V
O(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop, the load transient response is tested. The output capacitor
must supply all of the load current during the time between the application of the load transient and the turn on of
the P-channel MOSFET. VO immediately shifts by an amount equal to ΔI(LOAD) × ESR, where ESR is the
effective series resistance of CO. ΔI(LOAD) begins to charge or discharge CO generating a feedback error signal
used by the regulator to return VO to its steady-state value.
During this recovery time, VO is monitored for settling time, overshoot, or ringing that helps judge the converter
stability. Without any ringing, the loop has usually more than 45
° of phase margin.
Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET
rDS(on)) that are temperature dependant, the loop stability analysis must be performed over the input voltage
range, load current range, and temperature range.
Copyright 2006–2008, Texas Instruments Incorporated
35