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| 型号： | TPS62354YZG |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 1.6 A SWITCHING REGULATOR, 3350 kHz SWITCHING FREQ-MAX, BGA12 |
| 封装： | DSBGA-12 |
| 文件页数： | 22/46页 |
| 文件大小： | 1530K |
| 代理商： | TPS62354YZG |
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Voltage Scaling Management
V
NOM
(ROOF)
PWROK
OutputVoltageChangeInitiated
V
NOM
(FLOOR)
CompLowThreshold:V
NOM
(ROOF)
www.ti.com .............................................................................................................................................................. SLVS540E – MAY 2006 – REVISED APRIL 2008
In order to reduce the power consumption of the processor core, the TPS6235x can scale its output voltage.
There are two different strategies: 1) by software or 2) by hardware. It can be selected by the HW_nSW bit (more
information of the control and value bit mentioned below is shown in the Register Description section).
Synchronized Scaling Hardware Strategy (HW_nSW = 1)
The application processor programs via I2C the output voltages associated with the two states of VSEL signal:
floor (VSEL0) and roof (VSEL1) values. The application processor also writes the DEFSLEW value in the
CONTROL2 register to control the output voltage ramp rate.
These two registers can be continuously updated via I2C to provide the appropriate output voltage according to
the VSEL input. The voltage changes with the selected ramp rate immediately after writing to the VSEL0 or
VSEL1 register.
In PFM mode, when the output voltage is programmed to a lower value by toggling VSEL signal from high to low,
PWROK is defined as low, while the output capacitor is discharged by the load until the converter starts pulsing
to maintain the voltage within regulation.
In multiple-step mode, PWROK is defined as low while the output voltage is ramping up or down. Under all other
operating conditions, PWROK is defined to be low when the output voltage is below -1.5% of the target value.
Figure 52. PWROK Operation (Transition to a Lower Voltage)
Table 2 shows the output voltage states depending on VSEL0, VSEL1 registers, and VSEL signal.
Table 2. Synchronized Scaling Hardware Strategy Overview (HW_nSW = 1)
VSEL PIN
VSEL0 REGISTER
VSEL1 REGISTER
OUTPUT VOLTAGE
Low
No action
Floor
Low
Write new value
No action
Change to new value
Low
No action
Write
No change stays at floor voltage
High
No action
Roof
High
Write new value
No action
No change stays at roof voltage
High
No action
Write new value
Change to new value
Direct Scaling Software Strategy (HW_nSW = 0)
The digital processor writes the output voltage needed directly to the register VSEL1 via I2C interface. The
application processor also writes the DEFSLEW value in the CONTROL2 register to control the output voltage
ramp rate.
The voltage changes with the selected ramp rate after setting the GO bit in CONTROL2 register. This bit is reset
when the output voltage has reached its target value. In this mode, the output voltage change is independent of
VSEL signal and VSEL0 register is not used.
In PFM mode, when the output voltage is programmed to a lower value, PWROK is defined as low while the
output capacitor is discharged by the load until the converter starts pulsing to maintain the voltage within
regulation.
Copyright 2006–2008, Texas Instruments Incorporated
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