参数资料
型号: TPS62510DRCRG4
厂商: TEXAS INSTRUMENTS INC
元件分类: 稳压器
英文描述: 1.5 A SWITCHING REGULATOR, 1700 kHz SWITCHING FREQ-MAX, PDSO10
封装: 3 X 3 MM, GREEN, PLASTIC, SON-10
文件页数: 3/24页
文件大小: 1063K
代理商: TPS62510DRCRG4
DETAILED DESCRIPTION
Power Save Mode operation (MODE)
Power Save Mode Transition Thresholds
I
=
(PFM enter)
VIN
22 W
(1)
I
=
(PFM leave)
VIN
17 W
(2)
Output Voltage Tracking (OVT)
www.ti.com ................................................................................................................................................................ SLVS651A – MAY 2006 – REVISED JULY 2009
The TPS62510 has two target areas of operation. The high efficiency area is defined when the MODE pin is held
low. In this condition, the converter operates at typically 1.5-MHz fixed frequency PWM (pulse width modulation)
at moderate to heavy load currents. At light load currents, the converter automatically enters power save mode
and operates with PFM (pulse frequency modulation). Low noise operation is defined when the MODE pin is held
high. In this condition, the converter is forced into fixed frequency PWM mode and runs at 1.5 MHz. The
converter is capable of delivering 1.5-A output current.
The TPS62510 can also be synchronized to an external clock in the frequency range between 1.15 MHz and
2.25 MHz. Synchronization is aligned with the falling edge of the incoming clock signal. This allows simple
synchronization of two step-down converters running 180° out of phase reducing overall input RMS current.
During PWM operation, the converters use a unique fast response voltage mode control scheme with input
voltage feed-forward to achieve good line, and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is
turned on, and the inductor current ramps up until the comparator trips and the control logic turns off the switch.
The current limit comparator also turns off the switch if the current limit of the P-channel switch is exceeded.
After the adaptive dead time, which is used to prevent shoot through current, the N-channel MOSFET rectifier is
turned on, and the inductor current ramps down. The next cycle is initiated by the clock signal turning off the
N-channel rectifier, and turning on the P-channel switch.
When the MODE pin is connected to GND, the device automatically enters the power save mode when the
average output current reaches the appropriate threshold. This reduces the switching frequency and minimum
quiescent current, maintaining efficiency over the entire load current range. For low noise operation, the device
can be forced into fixed frequency PWM mode operating at 1.5 MHz over the entire load current range. This is
done by pulling the Mode pin high.
Many applications require a low output ripple voltage during power save mode. This is accomplished by a single
threshold PFM comparator which allows control of the output voltage ripple in power save mode. The larger the
output capacitor value, the smaller the output voltage ripple (see Figure 13). During power save mode, the device
monitors the output voltage with the PFM comparator. As soon as the output voltage falls below the nominal
output voltage, the device starts switching for a minimum of 1
s (typical), or until the output voltage is above the
nominal output voltage.
To achieve an accurate transition into and out of power save mode, the device monitors the average inductor
current which is equal to the average output current. The device enters power save mode when the average
output current is
≤ I(PFM enter) as calculated in Equation 1.
The device leaves the power save mode when the output current is
≥ I(PFM enter).
To minimize any delay times during a load transients, the device enters PWM mode when the output voltage is
2% below the nominal value, and the PFM/PWM transition comparator trips.
In applications where a processor or FPGA is powered, it is important that the I/O voltage and core voltage
start-up in a controlled way to avoid possible processor and FPGA latch-up. To implement this, the TPS62510
has an Output Voltage Tracking feature where the internal reference voltage for the error amplifier follows the
voltage applied to OVT, until OVT reaches Vref. Vref is the nominal internal reference voltage, typically 0.6 V. The
tracking feature is available with the fixed output voltage version as well as with the adjustable output voltage
version. Figure 18 shows a typical application where an external voltage (V1) is applied to OVT pin using a
resistor divider.
Copyright 2006–2009, Texas Instruments Incorporated
11
Product Folder Link(s): TPS62510
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