参数资料
型号: TPS62560DRVRG4
厂商: TEXAS INSTRUMENTS INC
元件分类: 稳压器
英文描述: 0.6 A SWITCHING REGULATOR, 2250 kHz SWITCHING FREQ-MAX, PDSO6
封装: 2 X 2 MM, 0.80 MM HEIGHT, GREEN, PLASTIC, SON-6
文件页数: 6/30页
文件大小: 1632K
代理商: TPS62560DRVRG4
SLVS815C – JANUARY 2008 – REVISED DECEMBER 2009
www.ti.com
DETAILED DESCRIPTION
OPERATION
The TPS62560/62 step-down converters operate with typically 2.25-MHz fixed-frequency pulse-width modulation
(PWM) at moderate to heavy load currents. At light load currents, the converter can automatically enter
power-save mode, and then operates in PFM mode. However, the TPS62561 operates with fixed-frequency
PWM only, also at light load conditions.
During PWM operation, the converter uses a unique fast-response voltage-mode control scheme with
input-voltage feed-forward to achieve good line and load regulation, allowing the use of small ceramic input and
output capacitors. At the beginning of each clock cycle initiated by the clock signal, the high-side MOSFET switch
is turned on. The current flows from the input capacitor via the high-side MOSFET switch through the inductor to
the output capacitor and load. During this phase, the current ramps up until the PWM comparator trips and the
control logic turns off the switch. The current-limit comparator also turns off the switch in case the current limit of
the high-side MOSFET switch is exceeded. After a dead time, which prevents shoot-through current, the low-side
MOSFET rectifier is turned on and the inductor current ramps down. The current flows from the inductor to the
output capacitor and to the load. It returns back to the inductor through the low-side MOSFET rectifier.
The next cycle is initiated by the clock signal again turning off the low-side MOSFET rectifier and turning on the
on the high-side MOSFET switch.
POWER-SAVE MODE
The power-save mode is enabled with the MODE terminal set to the low level. If the load current decreases, the
converter enters the power-save mode of operation automatically. During power-save mode, the converter skips
switching and operates with reduced frequency in PFM mode with a minimum quiescent current to maintain high
efficiency. The converter positions the output voltage typically 1% above the nominal output voltage. This voltage
positioning feature minimizes voltage drops caused by a sudden load step.
The transition from PWM mode to PFM mode occurs once the inductor current in the low-side MOSFET switch
becomes zero, which indicates discontinuous conduction mode.
During the power-save mode, the output voltage is monitored with a PFM comparator. As the output voltage falls
below the PFM comparator threshold of VOUT nominal + 1%, the device starts a PFM current pulse. The
high-side MOSFET switch turns on, and the inductor current ramps up. After the on-time expires, the switch is
turned off and the low-side MOSFET switch is turned on until the inductor current becomes zero.
The converter effectively delivers a current to the output capacitor and the load. If the load is below the delivered
current, the output voltage rises. If the output voltage is equal to or higher than the PFM comparator threshold,
the device stops switching and enters a sleep mode with typical 15-
μA current consumption.
If the output voltage is still below the PFM comparator threshold, a sequence of further PFM current pulses is
generated until the PFM comparator threshold is reached. The converter starts switching again once the output
voltage drops below the PFM comparator threshold.
With a fast single-threshold comparator, the output-voltage ripple during PFM-mode operation can be kept small.
The PFM pulse is time controlled, which allows modifying the charge transferred to the output capacitor by the
value of the inductor. The resulting PFM output-voltage ripple and PFM frequency depend primarily on the size of
the output capacitor and the inductor value. Increasing output capacitor values and inductor values minimizes the
output ripple. The PFM frequency decreases with smaller inductor values and increases with larger values.
The PFM mode is left and PWM mode entered in case the output current can no longer be supported in PFM
mode. The power-save mode can be disabled by setting the MODE terminal to high. The converter then operates
in the fixed-frequency PWM mode.
Dynamic Voltage Positioning
This feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. It is
active in power-save mode and regulates the output voltage 1% higher than the nominal value. This provides
more headroom for both the voltage drop at a load step, and the voltage increase at a load throw-off.
14
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): TPS62560 TPS62561 TPS62562
相关PDF资料
PDF描述
TPS62612YFD 1.2 A SWITCHING REGULATOR, 6600 kHz SWITCHING FREQ-MAX, BGA6
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