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参数资料
| 型号： | TPS62650YFFT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 1.7 A SWITCHING REGULATOR, 6600 kHz SWITCHING FREQ-MAX, BGA9 |
| 封装： | GREEN, DSBGA-9 |
| 文件页数： | 19/38页 |
| 文件大小： | 820K |
| 代理商： | TPS62650YFFT |
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Recognize START or
REPEATED START
Condition
Recognize STOP or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
Acknowledgement
Signal From Slave
SDA
SCL
MSB
P
Sr
or
P
S
or
Sr
START or
Repeated START
Condition
STOP or
Repeated START
Condition
Clock Line Held Low While
Interrupts are Serviced
1
2
7
8
9
ACK
1
2
3 8
9
ACK
Address
R/W
Slave Address
R/W
A
Register Address
A
Data
A
P
S
1
7
1
8
A = Acknowledge
S = START condition
P = STOP condition
From Master to TPS6265x
From TPS6265x to Master
“0” Write
Slave Address
R/W
A
Register Address
A
Data
A
P
S
1
7
1
8
A = Acknowledge
A = Not Acknowledge
S = START condition
Sr = REPEATED START condition
P = STOP condition
From Master to TPS6265x
From TPS6265x to Master
“0” Write
Sr
1
Slave Address
R/W
7
1
“1” Read
A
1
SLVS808A
– AUGUST 2009 – REVISED FEBRUARY 2011
Figure 53. Bus Protocol
TPS6265X I2C Update Sequence
The TPS6265x requires a start condition, a valid I2C address, a register address byte, and a data byte for a
single update. After the receipt of each byte, TPS6265x device acknowledges by pulling the SDA line low during
the high period of a single clock pulse. A valid I2C address selects the TPS6265x. TPS6265x performs an update
on the falling edge of the LSB byte.
When the TPS6265x is in hardware shutdown (EN pin tied to ground) the device can not be updated via the I2C
interface. Conversely, the I2C interface is fully functional during software shutdown (EN_DCDC bit = 0).
Figure 54.
" Write" Data Transfer Format in Standard, Fast- and Fast-Plus Modes
Figure 55.
" Read" Data Transfer Format in Standard, Fast- and Fast-Plus Modes
26
2009–2011, Texas Instruments Incorporated
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| TPS62651YFFT | 1.7 A SWITCHING REGULATOR, 6600 kHz SWITCHING FREQ-MAX, BGA9 |
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