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参数资料
| 型号： | TPS63020DSJ |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 4.5 A SWITCHING REGULATOR, 2600 kHz SWITCHING FREQ-MAX, PDSO14 |
| 封装： | 3 X 4 MM, PLASTIC QFN-14 |
| 文件页数： | 12/24页 |
| 文件大小： | 1403K |
| 代理商： | TPS63020DSJ |
SLVS916 – APRIL 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE DEVICE OPTIONS(1)
OUTPUT VOLTAGE
TA
PACKAGE MARKING
PACKAGE
PART NUMBER(2)
DC/DC
Adjustable
PS63020
TPS63020DSJ
–40°C to 85°C
14-Pin QFN
3.3 V
PS63021
TPS63021DSJ
(1)
Contact the factory to check availability of other fixed output voltage versions.
(2)
For detailed ordering information please check the PACKAGE OPTION ADDENDUM section at the end of this datasheet.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
Voltage range(2)
VIN, VINA, L1, L2, VOUT, PS/SYNC, EN, FB, PG
–0.3
7
V
Operating junction, TJ
–40
150
°C
Temperature range
Storage, Tstg
–65
150
°C
Human Body Model - (HBM)
3
kV
ESD rating(3)
Machine Model - (MM)
200
V
Charge Device Model - (CDM)
1.5
kV
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2)
All voltages are with respect to network ground terminal.
(3)
ESD testing is performed according to the respective JESD22 JEDEC standard.
THERMAL INFORMATION
TPS63020,
TPS63021
THERMAL METRIC(1)
UNITS
DSJ
14 PINS
qJA
Junction-to-ambient thermal resistance(2)
41.8
qJC(TOP)
Junction-to-case(top) thermal resistance (3)
47
qJB
Junction-to-board thermal resistance (4)
17
°C/W
yJT
Junction-to-top characterization parameter (5)
0.9
yJB
Junction-to-board characterization parameter (6)
16.8
qJC(BOTTOM)
Junction-to-case(bottom) thermal resistance (7)
3.6
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3)
The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5)
The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-board characterization parameter, yJB estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7)
The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
2
Copyright 2010, Texas Instruments Incorporated
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