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参数资料
| 型号： | TPS650250RHBR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC32 |
| 封装： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件页数： | 10/31页 |
| 文件大小： | 846K |
| 代理商： | TPS650250RHBR |
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DETAILED DESCRIPTION
STEP-DOWN CONVERTERS, VDCDC1, VDCDC2 AND VDCDC3
POWER SAVE MODE OPERATION
I
PFMDCDC1enter +
VINDCDC 1
24 W
I
PFMDCDC2enter +
VINDCDC 2
26 W
I
PFMDCDC3leave +
VINDCDC 3
39 W
(1)
SLVS843 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com
The TPS650250 incorporates three synchronous step-down converters operating typically at 2.25MHz fixed
frequency PWM (Pulse Width Modulation) at moderate to heavy load currents. At light load currents the
converters automatically enter Power Save Mode and operate with PFM (Pulse Frequency Modulation).
VDCDC1 delivers up to 1.6A, VDCDC2 and VDCDC3 are capable of delivering up to 0.8A of output current.
The converter output voltages can be programmed via the DEFDCDC1, DEFDCDC2 and DEFDCDC3 pins. The
pins can either be connected to GND, VCC or to a resistor divider between the output voltage and GND. The
VDCDC1 converter defaults to 2.8V or 3.3V depending on the DEFDCDC1 configuration pin, if DEFDCDC1 is
tied to ground the default is 2.80V, if it is tied to VCC the default is 3.3V. When the DEFDCDC1 pin is connected
to a resistor divider, the output voltage can be set in the range of 0.6V to VINDCDC1 V. Reference the section
on Output Voltage Selection for details on setting the output voltage range.
The VDCDC2 converter defaults to 1.8V or 2.5V depending on the DEFDCDC2 configuration pin, if DEFDCDC2
is tied to ground the default is 1.8V, if it is tied to VCC the default is 2.5V. When the DEFDCDC2 pin is
connected to a resistor divider, the output voltage can be set in the range of 0.6V to VINDCDC2 V.
On the DEFDCDC3 pin for the VDCDC3 converter, a resistor divider must be connected to set the output
voltage. This pin does not accept a logic signal like DEFDCDC1 or DEFDCDC2. The value for the resistor divider
can be changed during operation, so voltage scaling can be implemented by changing the resistor value.
During PWM operation the converters use a unique fast response voltage mode controller scheme with input
voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is
turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch.
The current limit comparator also turns off the switch in case the current limit of the P-channel switch is
exceeded. After the adaptive dead time used to prevent shoot through current, the N-channel MOSFET rectifier
is turned on and the inductor current ramps down. The next cycle is initiated by the clock signal again turning off
the N-channel rectifier and turning on the P-channel switch.
The three DC/DC converters operate synchronized to each other, with the VDCDC1 converter as the master. A
180° phase shift between the VDCDC1 switch turn on and the VDCDC2 and a further 90° shift to the VDCDC3
switch turn on decreases the input RMS current and smaller input capacitors can be used. This is optimized for a
typical application where the VDCDC1 converter regulates a Li-Ion battery voltage of 3.7V to 3.3V, the VDCDC2
converter from 3.7V to 2.5V and the VDCDC3 converter from 3.7V to 1.5V.
As the load current decreases, the converters enter Power Save Mode operation. During Power Save Mode the
converters operate in a burst mode (PFM mode) with a frequency between 1.125MHz and 2.25MHz for one burst
cycle. However, the frequency between different burst cycles depends on the actual load current and is typically
far less than the switching frequency, with a minimum quiescent current to maintain high efficiency.
In order to optimize the converter efficiency at light load the average current is monitored and if in PWM mode
the inductor current remains below a certain threshold, then Power Save Mode is entered. The typical threshold
to enter Power Save Mode can be calculated as follows:
During Power Save Mode the output voltage is monitored with a comparator and by maximum skip burst width.
As the output voltage falls below the threshold, set to the nominal VO, the P-channel switch turns on and the
converter effectively delivers a constant current as defined below.
18
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS650250
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