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DETAILED DESCRIPTION
Operation
DCDC1 Converter
DCDC2 Converter
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
The TPS6505x include each two synchronous step-down converters. The converters operate with 2.25-MHz
(typical) fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load
currents, the converters automatically enter Power Save Mode and operate with PFM (Pulse Frequency
Modulation).
During PWM operation the converters use a unique fast response voltage mode controller scheme with input
voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is
turned on, and the inductor current ramps up until the current comparator trips, and the control logic turns off the
switch. The current limit comparator turns off the switch if the current limit of the P-channel switch is exceeded.
After the adaptive dead time, which prevents shoot through current, the N-channel MOSFET rectifier is turned
on, and the inductor current ramps down. The next cycle is initiated by the clock signal turning off the N-channel
rectifier, and turning on the on the P-channel switch.
The two DC/DC converters operate synchronized to each other, with converter 1 as the master. A 180
° phase
shift between converter 1 and converter 2 decreases the input RMS current. Therefore, smaller input capacitors
can be used.
The converter 1 output voltage is set by an external resistor divider connected to FB_DCDC1 pin for TPS65050,
TPS65051 and TPS65054. For TPS65052, the output voltage is fixed to 3.3 V and this pin needs to be directly
connected to the output. See the Application Information section for more details. The maximum output current
on DCDC1 is 600 mA for TPS65050 and TPS65054. For TPS65051, TPS65052 and TPS65056, the maximum
output current is 1 A.
The VDCDC2 pin must be directly connected to the DCDC2 converter output voltage. The DCDC2 converter
output voltage is selected via the DEFDCDC2 pin.
TPS65050 and TPS65051: The output voltage is set with an external resistor divider. Connect the DEFDCDC2
pin to the external resistor divider.
TPS65052, TPS65054 and TPS65056: The DEFDCDC2 pin can either be connected to GND, or to VCC. The
converter 2 output voltage defaults to:
Device
DEFDCDC2 = low
DEFDCDC2 = high
TPS65052 , TPS65056
1 V
1.3 V
TPS65054
1.3 V
1.05 V
Copyright 2007, Texas Instruments Incorporated
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