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参数资料
| 型号： | TPS65182BRGZT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PQCC48 |
| 封装： | 7 X 7 MM, 0.9 MM, PLASTIC, QFP-48 |
| 文件页数： | 8/24页 |
| 文件大小： | 865K |
| 代理商： | TPS65182BRGZT |
SLVSAA2C – MARCH 2010 – REVISED OCTOBER 2010
www.ti.com
DATA TRANSMISSION TIMING
VBAT = 3.6 V ±5%, TA = 25C, CL = 100 pF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f(SCL)
Serial clock frequency
100
400
KHz
SCL = 100 KHz
4
s
Hold time (repeated) START condition. After this
tHD;STA
period, the first clock pulse is generated.
SCL = 400 KHz
600
ns
SCL = 100 KHz
4.7
tLOW
LOW period of the SCL clock
s
SCL = 400 KHz
1.3
SCL = 100 KHz
4
s
tHIGH
HIGH period of the SCL clock
SCL = 400 KHz
600
ns
SCL = 100 KHz
4.7
s
tSU;STA
Set-up time for a repeated START condition
SCL = 400 KHz
600
ns
SCL = 100 KHz
0
3.45
s
tHD;DAT
Data hold time
SCL = 400 KHz
0
900
ns
SCL = 100 KHz
250
tSU;DAT
Data set-up time
ns
SCL = 400 KHz
100
SCL = 100 KHz
1000
tr
Rise time of both SDA and SCL signals
ns
SCL = 400 KHz
300
SCL = 100 KHz
300
tf
Fall time of both SDA and SCL signals
ns
SCL = 400 KHz
300
SCL = 100 KHz
4
s
tSU;STO
Set-up time for STOP condition
SCL = 400 KHz
600
ns
SCL = 100 KHz
4.7
tBUF
Bus Free Time Between Stop and Start Condition
s
SCL = 400 KHz
1.3
SCL = 100 KHz
n/a
Pulse width of spikes which mst be suppressed
tSP
ns
by the input filter
SCL = 400 KHz
0
50
SCL = 100 KHz
400
Cb
Capacitive load for each bus line
pF
SCL = 400 KHz
400
16
Copyright 2010, Texas Instruments Incorporated
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