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| 型号： | TRF3750IPWRG4 |
| 厂商： | Texas Instruments |
| 文件页数： | 8/37页 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER PLL FREQ 16-TSSOP |
| 标准包装： | 2,000 |
| 类型： | PLL 频率合成器 |
| PLL： | 无 |
| 输入： | 时钟 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:1 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 2.4GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
| 配用： | TRF3750T-1900EVM-ND - TRF3750T-1900EVM TRF3750Q1900EVM-ND - TRF3750Q1900EVM 296-20836-ND - EVALUATION MOD FOR CDCM7005-QFN 296-20835-ND - EVALUATION MOD FOR CDCM7005-BGA 296-20834-ND - EVALUATION MOD FOR CDC7005-QFN |
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TRF3750
SLWS146B MARCH 2004 REVISED AUGUST 2007
www.ti.com
16
Phase Frequency Detector (PFD) and Charge Pump Stage
The outputs of the R divider and the N counter (please see pulse swallow section) are fed into the PFD stage, where
the two signals are compared in frequency and phase. The TRF3750 features an anti-backlash pulse, whose width
is controllable by the user, in order to optimize phase and spurious performance. The PFD feeds the charge pump,
which is the final output of the TRF3750. The charge pump output pulses need to be fed into an external loop filter,
which eventually produces the tuning voltage needed to control the external VCO to the desired frequency.
Pulse Swallow/Frequency Synthesis
The different stages of the TRF3750 enable the user to synthesize a large range of frequencies at the output of a
complete PLL. For a given reference frequency (fREFIN), the user’s choice of the R divider yields the PFD frequency
(fPFD), which is the step by which the resultant output frequency can be incremented or decremented. The choice
of prescaler, and A and B counters yields the output frequency at the external VCO (RFOUT) as shown below.
RFOUT = fPFD x N = (fREFIN / R) x (A + P x B)
MUXOUT Stage
The TRF3750 features a multiplexer that allows programmable access to several signals. Table 5 and Table 6 show
the truth tables. Some of the different signals available are detailed below.
Digital Lock Detect
This is an active high digital output that indicates when the device has achieved lock. The user can choose between
two precision settings for the lock detection, through the reference counter latch. A 0 on the lock detect precision
means that the digital lock detect output goes high only if three contiguous cycles of the PFD have an error of less
than 15 ns. A 1 would require five contiguous cycles (a more stringent condition). Any error of greater than 25 ns,
even on one cycle, would produce a 0 in the digital lock detect signal, indicating loss of lock.
Analog Lock Detect
Selecting the analog lock detect option at the output of the output multiplexer requires an external pull-up resistor
(≈10 k) to be placed on the output (MUXOUT, pin 14).
Fastlock Mode
The TRF3750 features two Fastlock Modes, which the user may select depending on the particular application.
There are two separate charge pump current settings (1 and 2) that can be programmed, and the Fastlock
Modes, when activated, enable the device to quickly switch from current setting 1 to current setting 2. The two
Fastlock Modes (1 and 2) differ in the way the device reverts back to current setting 1. In normal (steady-state)
operation, current setting 1 is used. For transient situations such as frequency jumps, current setting 2 can be
used.
Fastlock Mode 1
As soon as Fastlock Mode 1 is entered, the charge pump current is switched to the preprogrammed setting 2
and stays there until the charge pump gain programming bit is set to 0 in the N counter latch. This way, the user
has immediate software control of the transition between charge pump setting 1 and 2.
Fastlock Mode 2
As soon as Fastlock Mode 2 is entered, the charge pump current is switched to the preprogrammed setting 2
and stays there until the timer counter has expired. The timer counter is programmed by the user and counts
how many PFD cycles the device spends in current setting 2 in Fastlock Mode 2. The number of timer cycles
can be set in increments of four cycles in the range of 3 to 63. When the counter has expired, the device returns
to normal operation (fastlock disabled and charge pump current setting 1). This way no extra programming is
needed in order for the device to exit fastlock.
3-Wire Serial Programming
The TRF3750 features an industry-standard 3-wire serial interface that controls an internal 24-bit shift register.
There are a total of 3 signals that need to be applied: the clock (CLK, pin 11), the serial data (DATA, pin 12)
and the load enable (LE, pin13). The DATA (DB0DB23) is loaded MSB first and is read on the rising edge of
the CLK. The LE signal is asynchronous to the clock and at its rising edge the DATA gets loaded onto the
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相关代理商/技术参数 |
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| TRF3750IRGP | 功能描述:时钟合成器/抖动清除器 Hi Perform Integer-N PLL Freq Synthsizr RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| TRF3750IRGPG4 | 功能描述:时钟合成器/抖动清除器 Hi Perform Integer-N PLL Freq Synthsizr RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| TRF3750IRGPR | 功能描述:时钟合成器/抖动清除器 High Perf Integer-N PLL Freq Synth RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| TRF3750IRGPRG4 | 功能描述:时钟合成器/抖动清除器 High Perf Integer-N PLL Freq Synth RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| TRF3750Q1900EVM | 功能描述:射频开发工具 TRF3750Q1900 Eval Mod RoHS:否 制造商:Taiyo Yuden 产品:Wireless Modules 类型:Wireless Audio 工具用于评估:WYSAAVDX7 频率: 工作电源电压:3.4 V to 5.5 V |
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