参数资料
型号: TRF3761-AIRHATG4
厂商: TEXAS INSTRUMENTS INC
元件分类: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 104 MHz, PQCC40
封装: GREEN, PLASTIC, MO-220VJJD-2, QFN-40
文件页数: 35/60页
文件大小: 1736K
代理商: TRF3761-AIRHATG4
FUNCTIONAL DESCRIPTION
VCO
Divide by 2, by 4, and Output Buffer
N-Divider
OUT
F
200MHz
Prescalarnum
(3)
SLWS181J – OCTOBER 2005 – REVISED AUGUST 2008 ............................................................................................................................................... www.ti.com
B<12,0>: This 13-bit word <DB24,DB12> controls the value of the B counter of the N divider. The valid range is
from 3 to 8191.
A<5,0>: These 6 bits <DB11,DB6> control the value of the A counter. The valid range is from 0 to 63.
PRESC_MOD<1,0>: These bits <DB5,DB4> define the mode of the dual-modulus prescaler according to
START_LK: TRF3761 does not load the serial interface registers values into the dividers registers until bit DB29
of register 3 is set to 1. After TRF3761 is locked to the new frequency, bit DB29 is internally reset to 0.
Refer to Register 3 under the Application Information section.
The TRF3761 integrates a high-performance, LC tank, voltage-controlled oscillator (VCO). For each of the
devices of the TRF3761 family, the inductance and capacitance of the tank are optimized to yield the best
phase-noise performance. The VCO output is fed externally and to the prescaler through a series of very low
noise buffers, that greatly reduce the effect of load pulling onto the VCO.
To extend the frequency coverage, the TRF3761 integrates a divide by 2 and by 4 with a low noise floor. The
VCO signal is fed externally through a final open-collector differential-output buffer. This buffer is able to provide
up to 3dBm (typical) of power into a 200
differential resistive load. The open-collector structure gives the
flexibility to choose different load configurations to meet different requirements.
Prescaler Stage
This stage divides down the VCO frequency before the A and B counters. This is a dual-modulus prescaler
and the user can select any of the following settings: 8/9, 16/17, 32/33, and 64/65. Prescaling is used due to
the fact that the internal devices are limited in frequency operations of 200MHz. To determine the proper
prescaler value, Fout which is the frequency out of the VCO is divided by the numerator of the prescaler if
the answer is less than 200MHz then that is the prescalar to use, see Equation 3. If the value is higher than
200MHz then repeat this procedure with the next prescalar numerator until a value of 200MHz or less is
achieved. See the Synthesizing a Selected Frequency in the Section 10 Register 3.
A and B Counter Stage
The TRF3761 includes a 6-bit A counter and a 13-bit B counter that operate on the output of the prescaler.
The A counter can take values from 0 to 63, while the B counter can take values from 3 to 8191. Also, the
value for the B counter must be greater than or equal to the value for the A counter. The A and B counter
with the prescaler stage create the VCO N-divider, see Equation 4 and Equation 5. Refer to Synthesizing a
Selected Frequency in the Section 10 Register 3.
40
Copyright 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): TRF3761
相关PDF资料
PDF描述
TRF3761-EIRHAR PLL FREQUENCY SYNTHESIZER, 104 MHz, PQCC40
TRF3761-CIRHATG4 PLL FREQUENCY SYNTHESIZER, 104 MHz, PQCC40
TRF3761-JIRHATG4 PLL FREQUENCY SYNTHESIZER, 104 MHz, PQCC40
TRF3761-HIRHAT PLL FREQUENCY SYNTHESIZER, 104 MHz, PQCC40
TRF3761-EIRHAT PLL FREQUENCY SYNTHESIZER, 104 MHz, PQCC40
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