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| 型号： | TRF3761-DIRHARG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 104 MHz, PQCC40 |
| 封装： | GREEN, PLASTIC, MO-220VJJD-2, QFN-40 |
| 文件页数： | 39/60页 |
| 文件大小： | 1736K |
| 代理商： | TRF3761-DIRHARG4 |
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Synthesizing a Selected Frequency
Application Schematic
SLWS181J – OCTOBER 2005 – REVISED AUGUST 2008 ............................................................................................................................................... www.ti.com
The TRF3761 is an integer-N PLL synthesizer, and because of its flexibility (14-bit RDiv, 6-bit A counter, 13-bit B
counter, and dual modulus prescaler), is ideal for synthesizing virtually any desired frequency. If synthesizing a
900MHz local oscillator, with spacing capability (minimum frequency increment) of 200kHz, as in a typical GSM
application, the choice of the external reference oscillator is beyond the scope of this section. However, if a
10MHz reference is selected, the settings are calculated to yield the desired output frequency and channel
spacing. There is more than one solution to a specific set of conditions, so below is one way of achieving the
desired result. First, select the appropriate RDiv counter value. Since a channel spacing of 200kHz is desired,
the FPFD is set to 200kHz. Calculate the RDiv value through:
RDiv = FREFIN/FPFD = 10MHz/ 200kHz = 50.
Assume a prescaler value of 8/9 is selected. This is a valid choice, since the prescaler output is well within the
200MHz limit (900MHz / 8 = 112.5MHz). Select the appropriate A and B counter values.
RFOUT = FPFD × N = (FREFIN / RDiv) × (A counter + Prescalar numerator × B counter).
Therefore, the following equation must be solved:
900MHz = 200kHz x (A + 8 × B).
There are many solutions to this single equation with two unknowns; there are some basic constraints on the
solution, since 3
≤ B ≤ 8191, and also B ≥ A. So, if A = 4, solving the equation yields B = 562. One complete
solution would be to choose:
RDiv = 50, A counter = 4, Bcounter = 562 and Prescalar = 8/9
resulting in the desired N counter value = 4500. This is how the A counter, B counter and prescalar make up the
N counter.
When this procedure is complete the values for the N counter , R, and the prescalar ratio should be known.
Registers 2 and 3 need to be set up for operation of the chip. See Table 2 and Table 3 for this procedure.
Register 2 bits <DB30:DB18> 12:0 set the output frequency of the device along with register 3. See the N-Divider
section under the Functional Description.
Figure 87 shows a typical application schematic for the TRF3761. In this example, the output signal is taken
differential using the 2 resistive pull-up resistors of the final output buffer. A single-ended and tuned load
configuration is also available.
The loop filter components:
C1 = 303pF, R1 = 8.87k
, C2 = 1650pF, R2 = 3.4k, C3 = 330pF
are typical ones used for the plots shown above. Those values can be optimized differently according to the
requirements of the different applications.
44
Copyright 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): TRF3761
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TRF3761-DIRHAT | 功能描述:时钟合成器/抖动清除器 Low Noise Integer N PLL Freq Synth RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| TRF3761-DIRHATG4 | 功能描述:时钟合成器/抖动清除器 Low Noise Integer N PLL Freq Synth RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| TRF3761-E | 制造商:TI 制造商全称:Texas Instruments 功能描述:INTEGER-N PLL WITH INTEGRATED VCO |
| TRF3761-EIRHAR | 功能描述:时钟合成器/抖动清除器 Low Noise Integer N PLL Freq Synth RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| TRF3761-EIRHARG4 | 功能描述:时钟合成器/抖动清除器 Low Noise Integer N PLL Freq Synth RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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