参数资料
型号: TRF3761-EIRHARG4
厂商: TEXAS INSTRUMENTS INC
元件分类: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 104 MHz, PQCC40
封装: GREEN, PLASTIC, MO-220VJJD-2, QFN-40
文件页数: 41/60页
文件大小: 1736K
代理商: TRF3761-EIRHARG4
Loop Filter Design
SLWS181J – OCTOBER 2005 – REVISED AUGUST 2008 ............................................................................................................................................... www.ti.com
Numerous methodologies and design techniques exist for designing optimized loop filters for particular
applications. The loop filter design can affect the stability of the loop, the lock time, the bandwidth, the extra
attenuation on the reference spurs, etc. The role of the loop filter is to integrate and lowpass the pulses of the
charge pump and eventually yield an output tuning voltage that drives the VCO. Several filter topologies can be
implemented, including both passive and active. In this section, a third-order passive filter is used. For this
example, assume these several design parameters. The internal VCO has a value of 23MHz/V, meaning that in
the linear region, changing the tuning voltage of the VCO by 1V induces a change of the output frequency of
about 23MHz. It is known that N = 4500 and Fpfd = 200kHz from our previous example. It is assumed that
current setting in register 1 <DB7:DB5> is set to 100 and sets a maximum current of 5.6mA.TI recommends an
Icp of 5.6mA, which give the best spur performance, but can be changed for different application. In addition, the
bandwidth of the loop filter must be determined. This is a critical consideration as it affects the lock time of the
system. Assuming an approximate bandwidth of around 20kHz is required and that for stability a phase margin of
about 45 degrees is desired, the following values for the components of the loop filter can be derived. There is
almost an infinite number of solutions to the problem of designing the loop filter and the designer is called to
make tradeoff decisions for each application. Texas Instruments has provided a loopfilter program in the product
folder for the TRF3761.
Some terms are interchangeable and are described and equated here:
F
com = FPDF which identify the comparing frequency or phase detector frequency which is also equal to the
system channel step size. FOUT must be a multiple of Fcom.
F
min is the lower frequency of the design band.
F
max is the upper frequency of the design band.
F
ref is the reference frequency for the PLL. Fref must be a multiple of Fcom.
K
vco = Kv expressed in MHz per Volt (MHz/V) which is the gain of the VCO. The TRF3761 internal VCO has a
Kv = 23MHz/V.
I
cp is the charge pump current. The TRF3761 is typically set to 5.6mA.
F
c is the loop filter bandwidth which should be no more than 1/10 Fcom.
φ is phase margin in degrees. Values should be between 30 and 70. The higher the phase margin the better
the stability of the PLL but the slower the lock time. 45 degrees is a good tradeoff.
T3/T1 in percent is the percentage of the poles in the loop filter. Usually set to 45%. The higher the value
(closer to 100%) the more the spurs are attenuated, but peaking occurs in the pass band of the loop filter.
46
Copyright 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): TRF3761
相关PDF资料
PDF描述
TRF3761-DIRHAT PLL FREQUENCY SYNTHESIZER, 104 MHz, PQCC40
TRF3761-HIRHARG4 PLL FREQUENCY SYNTHESIZER, 104 MHz, PQCC40
TRF3761-FIRHAT PLL FREQUENCY SYNTHESIZER, 104 MHz, PQCC40
TRF3761-BIRHAR PLL FREQUENCY SYNTHESIZER, 104 MHz, PQCC40
TRF3761-KIRHAT PLL FREQUENCY SYNTHESIZER, 104 MHz, PQCC40
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