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| 型号： | TRF7961RHBT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC32 |
| 封装： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件页数： | 10/52页 |
| 文件大小： | 1023K |
| 代理商： | TRF7961RHBT |
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SLOU186F – AUGUST 2006 – REVISED AUGUST 2010
www.ti.com
Correlation between the RF input level and RSSI designation levels on the RX_IN1 and RX_IN2 are
Table 5-6 shows the RSSI level versus RSSI bit value. The RSSI has seven levels (3 bits each) with 4-dB
increments. The input level is the peak-to-peak modulation level of the RF signal as measured on one side
envelope (positive or negative).
Table 5-6. RSSI Level Versus Register Bit Value
RSSI
1
2
3
4
5
6
7
Input level
2 mVpp
3.2 mVpp
5 mVpp
8 mVpp
13 mVpp
20 mVpp
32 mVpp
As an example, from Table 5-7, let B2 = 1, B1 = 1, B0 = 0; this yields an RSSI value of 6. From Table 5-6
a Bit value of 6 would yield an RSSI level of 20 mVpp.
Table 5-7. RSSI Bit Value and Oscillator Status Register (0F)
Bit
Signal Name
Function
Comments
B7
Unused
B6
osc_ok
Crystal oscillator stable
B5
rssi_x2
MSB of auxiliary receiver RSSI
B4
rssi_x1
Auxiliary receiver RSSI
B3
rssi_x1
LSB of auxiliary receiver RSSI
4 dB per step
B2
rssi_2
MSB of main receiver RSSI
B1
rssi_1
Main receiver RSSI
B0
rssi_0
LSB of main receiver RSSI
5.2.2
Receiver – Digital Section
The received sub-carrier is digitized to form a digital representation of the modulated RF envelope. This
digitized signal is applied to digital decoders and framing circuits for further processing.
The digital part of the receiver consists of two sections, which partly overlap. The first section is the bit
decoders for the various protocols, whereas the second section consists of framing logic. The bit decoders
convert the sub-carrier coded signal to a bit stream and also to the data clock. Thus, the sub-carrier-coded
signal is transformed to serial data and the data clock is extracted. The decoder logic is designed for
maximum error tolerance. This enables the decoders to successfully decode even partly corrupted (due to
noise or interference) sub-carrier signals.
In the framing section, the serial bit-stream data is formatted in bytes. In this process, special signals like
the start of frame (SOF), end of frame (EOF), start of communication, and end of communication are
automatically removed. The parity bits and CRC bytes are checked and also removed. The end result is
clean or raw data, which is sent to the 12-byte FIFO register where it can be read by the external
microcontroller system.
The start of the receive operation (successfully received SOF) sets the flags in the IRQ and status
register. The end of the receive operation is indicated to the external system (MCU) by sending an
interrupt request (pin 13 IRQ). If the receive data packet is longer than 8 bytes, an interrupt is sent to the
MCU when the received data occupies 75% of the FIFO capacity to signal that the data should be
removed from the FIFO.
Any error in data format, parity, or CRC is detected, and the external system is notified of the error by an
interrupt-request pulse. The source condition of the interrupt-request pulse is available in the IRQ and
status register (address 0C). The bit-coding description of this register is given in Table 5-22.
18
System Description
Copyright 2006–2010, Texas Instruments Incorporated
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相关代理商/技术参数 |
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| TRF7961RHBT | 制造商:Texas Instruments 功能描述:RFID Reader IC |
| TRF7961RHBTG4 | 功能描述:RFID应答器 Multi-Standard High Freq RFID Read/Writ RoHS:否 制造商:Murata 存储容量:512 bit 工作温度范围:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
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| TRF7962ARHBR | 功能描述:RFID应答器 Fully Integ 13.56MHz RFID R/W IC RoHS:否 制造商:Murata 存储容量:512 bit 工作温度范围:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
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