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参数资料
| 型号： | TriCore |
| 厂商： | SIEMENS AG |
| 英文描述： | 32-bit microcontrollers(32位微控制器) |
| 中文描述： | 32位微控制器（32位微控制器） |
| 文件页数： | 17/17页 |
| 文件大小： | 117K |
| 代理商： | TRICORE |
How to use the
Watchdog Timer of the TriCore
17 of 17
AP3219 Rel.02
WDTPR
WDTSR[5]
R
0
1
Watchdog Reset Prewarning Flag.
Normal mode (default after reset).
A Watchdog error has occurred.
The Watchdog has issued an NMI trap and is in the final time-out phase
(WDTTO is also set in this case). A reset of the chip occurs after the time-out
has expired. This bit can be examined in the NMI trap routine to determine
the cause of the trap. WDTPR is cleared only through a reset.
WDTTO
WDTSR[4]
R
0
1
Watchdog Time-out Period Indication Flag.
Normal mode.
The Watchdog is operating in time-out mode (default after reset).
Time-out mode is entered automatically after a reset and after the first
password access to register WDTCON0 or when a Watchdog error is
detected. Time-out mode is terminated only in a non-error case with a modify
access to WDTCON0 writing ENDINIT to 1. After termination of the time-out
mode, WDTTO is cleared through hardware. If time-out mode is entered due
to a Watchdog error, this mode cannot be terminated until the Watchdog
reset occurs.
WDTDS
WDTSR[3]
R
0
1
Watchdog Enable/Disable Bit.
Watchdog Timer is enabled (default after reset).
Watchdog Timer is disabled.
This bit is updated with the state of bit WDTDR after ENDINIT is written to 1
during a modify access to register WDTCON0.
WDTIS
WDTSR[2]
R
0
1
Watchdog Input Clock Status Bit.
Watchdog Timer input clock is f SYSCLK /16384 (default after reset).
Watchdog Timer input clock is f SYSCLK /256.
This bit is updated with the state of bit WDTIR after ENDINIT is written to 1
during a modify access to register WDTCON0.
WDTOE
WDTSR[1]
R
0
1
Watchdog Overflow Error Status Flag.
No Watchdog overflow error.
An Watchdog overflow error has occurred.
This bit is set by hardware when the Watchdog Timer is enabled and is not
serviced before the overflow from 0xFFFF to 0x0000 occurs, or if the
Watchdog Timer is in time-out mode and the overflow occurs. This bit is only
reset through:
- a power-on, hardware, or software reset;
- after ENDINIT is written to 1 during a
modify access to register WDTCON0 (not possible if Watchdog is in the
reset prewarning Phase, WDTPR = 1).
WDTAE
WDTSR[0]
R
0
1
Watchdog Access Error Status Flag.
No Watchdog access error.
An Watchdog access error has occurred.
This bit is set by hardware when an illegal access to register WDTCON0 was
attempted (either a password or modifying access). This bit is only reset
through:
- a power-on, hardware, or software reset;
- after ENDINIT is written to 1 during a
modify access to register WDTCON0 (not possible if Watchdog is in the
reset prewarning phase, WDTPR = 1).
-
R
These bit positions are read-only, returning 0 when read. Writing to these bit
positions has no effect. These positions are reserved for future extensions,
and it is advised to always write a 0 to these bit positions when writing to the
register in order to preserve compatibility with future derivatives.
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