- 您现在的位置：买卖IC网 > PDF目录69525 > TRU050-GACCA12.032-6.016 (VECTRON INTERNATIONAL) PHASE LOCKED LOOP, CDSO16 PDF资料下载
参数资料
| 型号： | TRU050-GACCA12.032-6.016 |
| 厂商： | VECTRON INTERNATIONAL |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, CDSO16 |
| 封装： | HERMETIC SEALED, GULL WING, CERAMIC, SMT, DIP-16 |
| 文件页数： | 10/17页 |
| 文件大小： | 627K |
| 代理商： | TRU050-GACCA12.032-6.016 |
Vectron International 166 Glover Avenue, Norwalk, CT 06856-5160 Tel: 1-88-VECTRON-1 e-mail: vectron@vectron.com
Input NRZ Data Rates
Input RZ Data and Clock Rates 1
Nominal Output Frequency
Output 1
Output 2 2
Supply Voltage 3
Supply Current (VDD = 5.5 V)
Output Voltage Levels (VDD = 4.5 V)
Output Logic High 4
Output Logic Low 4
Transition Times: 4
Rise Time (0.5 V to 2.5 V)
Fall Time (2.5 V to 0.5 V)
Symmetry or Duty cycle 5
Output 1
Output 2
Recovered Clock
Input Data
Input Logic High
Input Logic Low
Control Voltage Bandwith (-3 dB,VC = 2.50 V)
Sensitivity @ VC = VO
Loss of Signal Indication 6
Output Logic High
Output Logic Low
Nominal Output Frequency on Loss of Signal: 7
Output 1
Output 2
Phase Detector Gain
DATAIN
OUT1
OUT2
VDD
IDD
VOH
VOL
tR
tF
SYM 1
SYM 2
RCLK
VIH
VIL
BW
F/VC
LOS
VOH
VOL
OUT1
OUT2
KD
0.008
12.0
0.05
4.5
25
2.5
-
0.5
40
45
40
2.0
-
50
2.5
-
-75 ppm
65.536
32.768
65.536
32.768
5.5
63
-
0.5
5
60
55
60
-
0.8
-
0.5
75 ppm
MHz
V
mA
V
ns
%
V
kHz
ppm/V
V
ppm from fo 1
ppm from fo 2
V/rad
1. For input RZ data, Manchester encoded data,
and input clock recovery applications, the
output clock must run at two times the input
rate to ensure that the input is clocked
correctly. Since the output clock has a max-
imum frequency of 65.536 MHz, these inputs
are limited to a maximum rate of 32.768 MHz.
2. OUT2 is a binary submultiple of OUT1, or
it may be disabled.
3. A 3.3 volt supply option is also available.
4. Figure 1 defines these parameters. Figure 2
illustrates the equivalent five-gate MTTL
load and operating conditions under which
these parameters are specified and tested.
5. Symmetry is the ON TIME/PERIOD in
percent with VS = 1.4 V for TTL, per figure 1.
6. A loss of signal (LOS) indicator is set to a
logic high if no transitions are detected at
DATAIN after 256 clock cycles. As soon
as a transition occurs at DATAIN, LOS is
set to a logic low.
7. Accuracy at room temperature. Stability
over temperature is typically –+ 20 ppm.
Parameter
Symbol
Min
Max
Unit
See Figure 11.
-0.53 x Data Density
Table 1.
Figure 1.
Figure 2.
2 of 17
相关PDF资料 |
PDF描述 |
|---|---|
| TRU050-GACHA44.736-22.368 | PHASE LOCKED LOOP, CDSO16 |
| TRU050-GALCA24.704-12.352 | PHASE LOCKED LOOP, CDSO16 |
| TRU050-GBLFA16.896-4.224 | PHASE LOCKED LOOP, CDSO16 |
| TRU050-GBLFA51.840-12.960 | PHASE LOCKED LOOP, CDSO16 |
| TRU050-GDCFA32.768-2.048 | PHASE LOCKED LOOP, CDSO16 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TRU050-GACFA | 制造商:未知厂家 制造商全称:未知厂家 功能描述:SINGLE DROP IN QUARTZ STABILIZED PLL SOLUTUION |
| TRU050GACGA | 制造商:Vectron International 功能描述: |
| TRU050-GACGA | 制造商:未知厂家 制造商全称:未知厂家 功能描述:SINGLE DROP IN QUARTZ STABILIZED PLL SOLUTUION |
| TRU050-GACGA-1M0000000 | 制造商:VECTRON 制造商全称:Vectron International, Inc 功能描述:Complete VCXO based Phase-Locked Loop |
| TRU050GACGA20.4800MHZ | 制造商:Vectron International 功能描述: |
发布紧急采购，3分钟左右您将得到回复。