参数资料
型号: TRU050-TACCA38.880-19.440
厂商: VECTRON INTERNATIONAL
元件分类: PLL合成/DDS/VCOs
英文描述: PHASE LOCKED LOOP, CDIP16
封装: HERMETIC SEALED, CERAMIC, DIP-16
文件页数: 7/17页
文件大小: 627K
代理商: TRU050-TACCA38.880-19.440
If the DATAIN input to the phase detector is a clock signal, the VCXO, or the divided VCXO output fed back to CLKIN, must
be twice the DATAIN rate. In figure 20, the 2.048 MHz system reference clock can be treated as a 4.096 MHz NRZ data
stream with a data density of 100%. Therefore, the feedback frequency in the PLL would be 4.096 MHz (the 32.768
MHz clock frequency divided by 8).
Vectron International 166 Glover Avenue, Norwalk, CT 06856-5160 Tel: 1-88-VECTRON-1 e-mail: vectron@vectron.com
Figure 20.
Figure 21.
Figure 22.
Another example would be to translate 8.000 kHz to 51.840 MHz.
15 of 17
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