参数资料
型号: TRU050-TDCFA16.000-1.000
厂商: VECTRON INTERNATIONAL
元件分类: PLL合成/DDS/VCOs
英文描述: PHASE LOCKED LOOP, CDIP16
封装: HERMETIC SEALED, CERAMIC, DIP-16
文件页数: 5/17页
文件大小: 627K
代理商: TRU050-TDCFA16.000-1.000
Applications
The three key applications for the TRU-050 are clock recovery of digital data, frequency translation and clock
smoothing. These timing needs are required by a wide variety of markets such as telecommunications,
datacommunications, digital video and audio, telemetry, test equipment and sensing.
Clock Recovery and Data Retiming
The TRU-050 was designed to recover a clock imbedded in an NRZ data signal, and retime it with a data pattern. In
this application, the VCXO frequency is exactly the same as the NRZ data rate and the outputs are taken off Pin 11
(Recovered Clock) and Pin 12 (Recovered Data). The diagram below shows a typical circuit.
Figure 17 shows the relationship between DATAIN (Pin 7) and CLKIN (Pin 9) under locked conditions. The rising edge
of the CLKIN is centered to the DATAIN pulse.
Vectron International 166 Glover Avenue, Norwalk, CT 06856-5160 Tel: 1-88-VECTRON-1 e-mail: vectron@vectron.com
Figure 16.
Figure 17.
13 of 17
Is Vectron ISO
registered?
Yes! Vectron’s
quality system was
registered to ISO
9001 in October 1996.
How Is It Used?
Relationship of RCLK (Pin 11) and RDATA (Pin 12). The falling edge of the Recovered Clock is in the middle of the
data pattern and should be used to clock the data into the next part of the circuit. There is a one and a half cycle
delay (frequency of Pin 9) between DATAIN and RDATA. Therefore a 10 MHz signal would have a 150 nS delay
between DATAIN and RDATA plus additional circuit delays, which are typically 9 nS.
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